RF Front-End PCB Design
Thought
Work done
- Began the SAR RF front-end migration and successfully removed the legacy Artix-7 FPGA (U11) and obsolete FT230X USB-UART bridge (IC1).
- Added the new iCE40UP5K-SG48 FPGA (U11), FT2232H USB FIFO (IC1), USBLC6-2P6 USB ESD protection (U13), USB-C CC pull-downs, reset support, and decoupling/bulk capacitors.
- Reworked USB-C connectivity so VBUS is on a new +5V_USB net instead of the RF 3.3V rail, added CC1/CC2 5.1kΩ pull-downs, and connected USB D+/D− through the ESD device to the FT2232H.
- Connected the ADC D0-D7 bus and ADC clock to the new iCE40 FPGA, restored SPI flash connectivity to the FPGA, and created the FT2232H FIFO data/control interface nets.
- ✅ Legacy Artix-7 FPGA removed from the schematic and replaced with iCE40UP5K-SG48.
- ⚠️ PCIe cleanup was started, but I could not complete/verify all PCIe connector/circuit/net removal before execution stopped.
- ✅ FT2232H and USB ESD support were added and wired at the schematic level.
- ✅ USB-C VBUS power-net issue was corrected from the observed RF 3.3V tie to a dedicated +5V_USB net.
- ⚠️ Board was previously verified as 70 mm x 50 mm, 4-layer, L2 GND / L3 power, but I could not complete the final layout placement/routing pass.
- ⚠️ ERC/DRC validation could not be completed after the migration edits.
- Continue by verifying/removing any remaining PCIe/FPC artifacts and orphan PCIe nets, then place the new iCE40/FT2232H/USB support components in the required left-to-right layout zones and run ERC/DRC cleanup. After schematic cleanup, proceed to PCB layout placement/routing on the existing 70 mm x 50 mm 4-layer board.
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Layout Optimization Status
Completed
- Resized the PCB outline to 70 mm × 50 mm with 2 mm corner radius and 0.2 mm board inset/keepout.
- Applied a Standard 4 Layer (Custom) stackup:
- Top Copper: Signal
- Mid-Layer 1: Ground Plane
- Mid-Layer 2: Power Plane
- Bottom Copper: Signal
- Configured the GND net with 2 mm × 2 mm fill stitching density and 1 mm × 1 mm stitching offset to support RF stitching via generation around the RF chain.
- Reworked component placement into functional zones on the 70 mm × 50 mm board:
- RF inputs / front-end at left: J2, J3, U5, U6, U7, U8
- IF and ADC center-left/center: U9, U10
- FPGA center: U11
- USB/digital right side: IC1, J4, J5
- Power components along top edge: J1, U1, U2, U3, U4
- Final major-component placement fit is approximately 69.3 mm × 48.65 mm, inside the 70 mm × 50 mm board.
- Fixed the AD8331 U9 missing-power ERC condition. U9 VIN is no longer tied to a supply; it is biased with U9 VCM on net
U9_VIN_VCM_BIAS, and the U9 supply pins are connected to the main input supply rail path.
Verification Results
- Stackup verification: passed for 4 copper layers with Mid-Layer 1 configured as Ground Plane.
- Missing footprints: passed.
- Invalid layer assignments: passed.
- Missing power ERC: passed.
- Placement: all 68 components are placed on the top layer inside the 70 mm × 50 mm outline with no reported component overlaps/out-of-bounds from placement cleanup.
Remaining Issues
- DRC still reports 4 overlapping copper errors, all associated with pad group/component UID
61a06793, which corresponds to the USB interface component IC1 area. This likely requires pad/footprint-level inspection or manual copper adjustment. - I attempted a footprint-level cleanup by disabling four unnamed IC1 mount pads, but the overlapping-copper review still reports the same four IC1-area errors. The remaining issue appears to require deeper footprint/pad geometry correction or replacement of the USB interface footprint.
- DRC still reports 140 airwires. This is expected because the requested workflow avoided a full-board autoroute; the layout remains intentionally unrouted.
- ERC still reports 269 floating-pin warnings, mostly on spare FPGA pins, RF/PLL control pins, ADC references/control pins, connector pins, and unused interface pins. These need pin-by-pin triage: connect required pins and mark true unused pins as no-connect.
- The project still contains the existing XC7A12T/FT230X-style architecture rather than a fully replaced iCE40 + FT2232H schematic. The layout work preserved the current schematic functionality as requested, but a true iCE40/FT2232H migration would require a separate schematic replacement and re-routing pass.
Recommended Next Steps
- Inspect and repair IC1/pad
61a06793overlapping copper. - Decide whether to perform full-board routing; if yes, route power first, then RF/clock/ADC paths, then USB/digital, then remaining control nets.
- Triage floating pins with datasheets and add no-connect markers for intentionally unused pins.
- If the final target is truly iCE40 + FT2232H rather than the current XC7A12T/FT230X design, perform a schematic migration before final routing.
Completed
Verification Results
Remaining Issues
Recommended Next Steps
