Schematic Build Progress
Date: 2026-08-20
Scope: INTERCEDE controller schematic only; PCB layout not started.
Completed in this build pass
- Replaced the stale unconnected 54-component scaffold with exact locked primary parts and authoritative reference designators.
- Placed 90 components across power, MCU/ESP32, Ethernet, memory/RTC/security, USB, isolated serial, Stage 11 machine I/O, and the canonical LM5155/TPS23861 PoE section.
- Built and wired Stage 1 input protection (
J1, D1, U1, Q1, C1) for the approved ATX input range.
- Built and wired the locked U2 +5 V and U3 +3.3 V buck circuits through their output and feedback networks.
- Built and fully wired the supplied J8/J9 PC817C machine-I/O circuits, including
MACH_COM, fixed polarity, current-limit resistors, pull-ups/pull-downs, connector NC pins, and named logic nets.
- Built the isolated serial power domains, three ADuM1201 paths, two MAX3232 paths, J4/J5/J6 connector channels, U17 receive tri-state mux, charge-pump networks, and explicit
ISO_GND.
- Built the USB-C CC, shield, ESD, and USB 2.0 data path to ESP32-S3.
- Restored
U28 TPS23861PWR and U29 LM5155DSSR as the canonical unresolved PoE power section.
- Added the Rev-B
>=2.5 kV isolated-converter upgrade TODO to both locked RBE-0505S instances while retaining them for Rev A.
Verification evidence
- Current schematic: 90 components, 90 named nets.
- Current schematic after the approved continuation pass: 105 components with power, serial, USB, clock, and decoupling additions.
GND, ISO_GND, MACH_COM, and CHASSIS were inspected directly and remain four distinct nets.- Stage 11 machine-side pins connect only through PC817C isolation; no
MACH_COM to logic-ground bridge was created.
- No PCB placement, routing, stackup, or manufacturing export was performed.
Remaining before schematic completion
Completion status
The schematic electrical review is now clean. A fresh ERC pass at 2026-08-20T12:23Z returned zero ERROR, WARNING, or OPEN checks for floating pins, single-pin nets, no-connect handling, power pins, driver conflicts, pin-to-pin conflicts, shorted components, and undriven nets. Passive/component checks also returned no open findings.
Final continuation work
- Added and wired locked
BT1 XDCR-2032-603 to the DS3231 VBAT rail.
- Assigned ATmega machine I/O and serial-mux GPIOs exactly as approved; SAS remains intentionally unswitched.
- Implemented Q3/Q4 COM isolator supply switching and connected their gates to the approved select nets.
- Implemented the reviewed Q2 USB-VBUS PMOS choice and D2 protected test node with TP1; review notes are stored on the components.
- Wired the locked J7 2x10 map, including AVR ISP, ESP UART/EN/GPIO0, bench rails, grounds, and NC test points 15-18.
- Added ESP32 remote ATmega ISP capability: shared MOSI/MISO/SCK, runtime
AVR_SPI_SS, and ESP GPIO-controlled AVR_RESET.
- Allocated non-strapping ESP32 GPIOs for both W5500s and the TPS23861 control interface.
- Completed the controller-side Mode-B TPS23861 port using a 100V pass MOSFET, 0.255-ohm Kelvin shunt, drain/SEN resistors, fuse, 58V TVS, and 100V port capacitor.
- Completed the LM5155 12V-to-54V boost schematic using TI's reference design, with a 100V MOSFET/Schottky, 18.5A-class 6.8uH inductor, 8mohm shunt, 54V feedback divider, UVLO, compensation, soft-start, timing, current-sense filter, PGOOD, and 100V output capacitors.
- Final BOM audit: 44 unique part groups and 169 instances. Exact TI-reference MPNs were attached to the LM5155 control-loop passives; high-voltage bulk/ceramic capacitor production MPN selection remains a pre-layout sourcing task, not an electrical schematic blocker.
- Final netlist audit confirmed
GND, ISO_GND, MACH_COM, and CHASSIS remain distinct and the remote-programming SPI/reset nets include U4, U5, J7, and F-RAM as intended.
No PCB layout, placement, routing, stackup, or manufacturing export was started.
Continuation-pass additions
- Wired ATmega +5 V supplies, 16 MHz crystal, load capacitors, AREF bypass, and one decoupler per supply/reference pin.
- Wired ESP32-S3 3.3 V/ground, EN pull-up, external decoupling, and USB D+/D- through the USBLC6-2SC6.
- Added exact locked X1/X2 crystal components from public part evidence.
- Confirmed the ATX input conditions and retained the locked RBE-0505S parts with the Rev-B >=2.5 kV upgrade note.
- ATmega power/clock/reset/decoupling and final 5 V versus 3.3 V bus-level treatment.
- ESP32 EN/boot/decoupling and assignment of unresolved control GPIO nets.
- FRAM/RTC/ATECC power, SPI/I2C, backup battery, and pull-ups.
- Both W5500 mandatory bias, decoupling, crystal, PHY/magnetics/RJ45 wiring and independent CS/INT/RST nets.
- J7 debug mapping and the unresolved purposes of Q2/D2/L3.
- Q3/Q4 hardware interlock controls and attachment of the three U17 OE nets to approved MCU pins.
- LM5155 high-voltage support network and TPS23861 per-port MOSFET/sense/protection/injection circuitry.
- Placement/legibility cleanup and final ERC fix/waiver pass.
Localized unresolved notes
U28 Role Details identifies the missing external TPS23861 port circuit.U29 Role Details identifies the missing locked LM5155 support network.U15/U16 Role Details carry the Rev-B isolation upgrade TODO.J7, Q2, and D2 Role Details identify unresolved mappings/functions rather than silently guessing.