Hardware Prototype Planning
custom-4-layer:custom-4-layer to the board.Table
| Item | Status | Result / blocker |
|---|---|---|
| 1. Isolated 5 V rail power findings | Completed | ISO_5V_SAS and ISO_5V_COM are now explicitly typed as Power. Existing RBE-0505S connectivity was verified: U15/U16 +Vout drive their respective isolated rails and both -Vout pins return only to ISO_GND. GND, ISO_GND, and CHASSIS remain separate. |
2. DS3231 backup and ~RST | Failed / blocked by required choices | BOM contains no backup cell, holder, or supercapacitor. U9 Role Details mention “CR2032 backup,” but this is not an exact orderable cell/holder selection, so none was invented. VBAT remains open. ~RST remains open because the datasheet describes an open-drain reset/power-fail pin requiring a pull-up when used, but project intent does not define its use and the datasheet evidence did not explicitly authorize an NC marker. |
| 3. Safe no-connect cleanup | Partial completed | Marked U15/U16 pin 4 NC per RBE datasheet. Removed unused U2/U3 PGOOD nets and marked PG no-connect; TI explicitly states PG must be left floating when unused. Connected JD’s two shell terminals to CHASSIS for the exact shielded, non-LED RJ45. No MCU GPIO was marked NC because canonical documents explicitly leave the resource map unresolved. |
| 4. Orphan optional components | Completed review; none removed | Q2 and D2 have documented unresolved USB/service roles; Q3/Q4 have documented serial interlock roles. They are not BOM-less or intent-less placeholders, so removal would violate the bounded scope. |
| 5. J7 | Completed as constrained | Left untouched. All 20 pins still require a service/debug mapping, or J7 should be removed by an explicit design decision. |
| 6. Undocumented GPIO assignments | Completed as constrained | No W5500 SPI/INT/RST, ATmega↔ESP32, serial-select, FRAM CS, or TPS23861 control assignments were invented. |
| 7. LM5155/TPS23861 | Completed as constrained | No compensation, current-sense, switching power stage, PSE FET, or 54 V injection circuitry was improvised. |
| 8. Fresh ERC | Completed | Fresh ERC reduced from 133 to 126 findings: 122 floating pins, 1 missing-power finding, 3 single-pin nets. |
VBAT contributes both one floating-pin finding and one missing-power finding.Table
| Group | Findings | Included issues |
|---|---|---|
| Service connector mapping | 20 | J7 pins 1–20. |
| MCU GPIO/resource map | 76 | 26 ATmega pins (including reset), 34 ESP32 pins, 12 dual-W5500 SPI/INT/RST pins, FRAM ~CS, and three U17 serial-select single-pin nets. |
| PoE boost/PSE design | 16 | Seven LM5155 support pins, five TPS23861 port/control pins, and JD spare-pair contacts 4/5/7/8. |
| Optional support parts | 14 | Q2 (3), D2 (2), Q3/Q4 (6), DS3231 ~RST (1), and DS3231 VBAT counted as floating plus missing power (2 findings). |
| Harmless unused pins | 0 | All unambiguous unused pins addressed in this bounded pass are now explicitly treated; no remaining finding was safely classifiable as harmless without an unresolved design choice. |
| Total | 126 | 122 floating + 1 missing power + 3 single-pin nets. |
DS3231SN#T&R exposes physical package pins 5–12 as duplicate GND terminals rather than N.C. pins. All nine displayed GND terminals are currently on GND, and inspection does not provide pin-number mapping to identify the real pin 13 ground safely. No blind disconnect was attempted. A part-quality report was filed with Flux engineering.ISO_5V_SAS: U15 +Vout, U10 VDD2, U11 VCC, C30.ISO_5V_COM: U16 +Vout, U12/U13 VDD2, U14 VCC, C35.ISO_GND: U15/U16 -Vout plus isolated-side returns only.CHASSIS: USB shell, J3 shell, and JD shell terminals.Scope status
Exact remaining findings grouped by decision area
RTC library blocker
Verification evidence