Created the datasheet-backed CH592F QFN-28 component and completed the 42-component schematic with dual isolated CR2450 cells, BLE RF/clock/debug circuitry, and SSD1680 E-Ink logic interface. The external 15 V converter was removed; final ERC and passive checks report no open issues.
Open item
The panel datasheet image does not clearly expose two charge-pump diode junctions, so D4/D5 remain intentionally unconnected. The design is not ready for PCB release until confirmed from a clear GDEY0213B74 reference schematic.
Next steps
Provide a clear panel reference schematic or manufacturer application circuit to finish D4/D5.
Review the schematic pin assignments.
Proceed to PCB sizing and component placement once the bias circuit is confirmed.
I’ll locate an authoritative or clearly legible GDEY0213B74/SSD1680 reference circuit, resolve the exact D4/D5 junctions, update the schematic, and re-run connectivity/ERC checks.
I prepared the research-and-fix plan, but execution stopped because no ACUs are currently available. The schematic remains unchanged: D4/D5 are still intentionally unconnected, and no guessed charge-pump wiring was added.
Remaining work:
Locate and cross-check a clear official GDEY0213B74/SSD1680 reference circuit.
Wire and orient D4/D5.
Verify the complete bias network and rerun ERC.
Update the specification and bring-up plan with the sourced topology.
Battery-powered BLE electronic shelf label using a WCH CH592F QFN-28 MCU and GDEY0213B74 2.13-inch SSD1680 raw E-Ink panel. Status: schematic review.
System Architecture
Two CR2450 cells feed individual PMEG2005EJ isolation diodes, a master switch, and VBAT_SW. CH592F runs directly from this rail. A SiP32431 load switch powers only panel VCI/VDDIO. The panel's SSD1680 GDR/RESE external network generates VGH/VGL/VSH/VSL/VCOM locally. There is no external 15 V rail.
Hardware Subsystems
Dual TE/Linx BAT-HLD-006-SMT CR2450 holders, individually diode-isolated to prevent cross-charge.
CH592F QFN-28 4x4 mm, 0.4 mm pitch, exposed ground pad; custom part derived from WCH CH592DS1 V1.8.
TE 2-1734839-4 24-position 0.5 mm top-contact FPC connector.
GDEY0213B74 bias support: 47 uH, Si1308EDL, 2.2 ohm RESE sense, MBR0530-class diodes, 1 uF/25 V reservoirs on generated HV nodes.
Samtec FTSH-103-01-L-DV debug connector exposing VBAT_SW, TCK, TIO, RESET_N and ground.
Interfaces and Pin Mapping
Table
Function
CH592F pin
Net
SPI SCLK
PA13
EPD_SCLK
SPI MOSI
PA14
EPD_MOSI
CS#
PA12
EPD_CS_N (10k pull-up)
D/C#
PB7
EPD_DC
RES#
PB4
EPD_RESET_N (10k pull-up)
BUSY
PB22
EPD_BUSY
Panel power enable
PA9
EPD_PWR_EN (pull-down)
Debug clock/data
PB15/PB14
DBG_TCK/DBG_TIO
Reset
PB23
MCU_RESET_N
Power and Runtime Expectations
No charger. A fresh CR2450 is about 3.0 V; Schottky and switch drop leave about 2.7-2.9 V, within CH592F 1.7-3.6 V and panel VCI 2.2-3.7 V. Near end of discharge, panel refresh becomes the limiting condition before the MCU minimum.
Table
Mode/load
Estimated source current
CH592F power-down
0.3-1.3 uA
Panel deep sleep / switched off
load-switch leakage plus GPIO leakage, target <1 uA
BLE receive
~3.5 mA
E-Ink logic/refresh average
~3.5 mA, with higher short booster pulses
Conservative system sleep target
3-8 uA
Two nominal 600 mAh cells provide 1200 mAh theoretical capacity. At 8 uA static the idealized limit is ~17 years, but battery shelf life dominates. At 20 uA long-term average, ideal runtime is ~6.8 years; use 3-5 years as a preliminary product estimate pending measured BLE duty cycle, refresh waveform, temperature, cell ESR, and self-discharge. Reservoir capacitance is provided for pulse support.
Important Design Decisions
Removed standalone 15 V boost completely.
Panel high voltages are generated only by the documented SSD1680 integrated-bias external network and never connect to MCU logic.
32 MHz crystal is mandatory; no external load capacitors because CH592F provides programmable internal load capacitance.
Unused MCU pins are marked no-connect.
Open Validation Items
Confirm exact panel charge-pump diode interconnection against the original figure artwork before PCB release; OCR text exposes values but not every crossing/junction reliably.
Bench-check FPC contact orientation and effective MLCC capacitance at 18-20 V.
Tune antenna matching and crystal load register on assembled boards.
Change Notes
Removed all external-15-V requirements, selected CH592F QFN-28, implemented panel-integrated bias architecture, updated power/runtime assumptions, and recorded final firmware pin map.