BLE ESL Board Design


Created the datasheet-backed CH592F QFN-28 component and completed the 42-component schematic with dual isolated CR2450 cells, BLE RF/clock/debug circuitry, and SSD1680 E-Ink logic interface. The external 15 V converter was removed; final ERC and passive checks report no open issues.
Open item
  • The panel datasheet image does not clearly expose two charge-pump diode junctions, so D4/D5 remain intentionally unconnected. The design is not ready for PCB release until confirmed from a clear GDEY0213B74 reference schematic.
Next steps
  1. Provide a clear panel reference schematic or manufacturer application circuit to finish D4/D5.
  2. Review the schematic pin assignments.
  3. Proceed to PCB sizing and component placement once the bias circuit is confirmed.
Please find a clearer GDEY0213B74 reference schematic and finish the D4/D5 charge-pump wiring.
I’ll locate an authoritative or clearly legible GDEY0213B74/SSD1680 reference circuit, resolve the exact D4/D5 junctions, update the schematic, and re-run connectivity/ERC checks.
I prepared the research-and-fix plan, but execution stopped because no ACUs are currently available. The schematic remains unchanged: D4/D5 are still intentionally unconnected, and no guessed charge-pump wiring was added.
Remaining work:
  • Locate and cross-check a clear official GDEY0213B74/SSD1680 reference circuit.
  • Wire and orient D4/D5.
  • Verify the complete bias network and rerun ERC.
  • Update the specification and bring-up plan with the sourced topology.
Research D4/D5 wiring
Search relevant datasheets
Inspect charge-pump nets

Firmware Getting Started
Toolchain
Use the official Apache-2.0 openwch/ch592 SDK/HDK and WCH MounRiver Studio or the SDK's GCC-compatible project structure. Start from an official CH592 BLE example and retain its vendor BLE library/linker script.
Final Pin Map
  • PA13: SPI0 SCK -> EPD_SCLK
  • PA14: SPI0 MOSI -> EPD_MOSI
  • PA12: GPIO output -> EPD_CS_N
  • PB7: GPIO output -> EPD_DC
  • PB4: GPIO output -> EPD_RESET_N
  • PB22: GPIO input -> EPD_BUSY
  • PA9: GPIO output -> EPD_PWR_EN
  • PB15/PB14: TCK/TIO debug
  • PB23: active-low reset
Startup Sequence
  1. Initialize clock from mandatory 32 MHz crystal; set CH592 internal crystal load capacitance for the selected crystal after measurement.
  2. Enable internal DC-DC using the official SDK's documented DCDC_ENABLE path.
  3. Drive CS#, RESET# high and EPD_PWR_EN low before configuring SPI.
  4. Configure SPI0 mode per SSD1680 timing; MOSI-only is sufficient.
  5. Enable EPD power, delay for rail settling, reset panel, wait BUSY deassertion, then send SSD1680 initialization/LUT sequence from the Good Display sample.
  6. After refresh, send deep-sleep command, set SPI/control pins low or high-impedance per datasheet, then disable EPD_PWR_EN to avoid back-power.
Starter Skeleton

C


#include "CH59x_common.h"

#define EPD_CS_LOW()    GPIOA_ResetBits(GPIO_Pin_12)
#define EPD_CS_HIGH()   GPIOA_SetBits(GPIO_Pin_12)
#define EPD_PWR_ON()    GPIOA_SetBits(GPIO_Pin_9)
#define EPD_PWR_OFF()   GPIOA_ResetBits(GPIO_Pin_9)
#define EPD_DC_DATA()   GPIOB_SetBits(GPIO_Pin_7)
#define EPD_DC_CMD()    GPIOB_ResetBits(GPIO_Pin_7)
#define EPD_RST_HIGH()  GPIOB_SetBits(GPIO_Pin_4)
#define EPD_RST_LOW()   GPIOB_ResetBits(GPIO_Pin_4)
#define EPD_BUSY()      GPIOB_ReadPortPin(GPIO_Pin_22)

static void epd_write(uint8_t value, int data) {
    if (data) EPD_DC_DATA(); else EPD_DC_CMD();
    EPD_CS_LOW();
    /* Confirm the exact official SDK SPI0 transmit identifier from the selected example;
       do not substitute an invented API. */
    // SPI0_MasterSendByte(value);
    EPD_CS_HIGH();
}

int main(void) {
    SetSysClock(CLK_SOURCE_PLL_60MHz);
    /* Keep SDK DCDC/clock calls aligned with the checked-out SDK revision. */
    EPD_CS_HIGH(); EPD_RST_HIGH(); EPD_PWR_OFF();
    while (1) { __WFI(); }
}
The GPIO macro names above follow public CH59x headers; the exact SPI send symbol and BLE initialization entry points must be taken unchanged from the checked-out official example revision.
  • Toolchain

  • Final Pin Map

  • Startup Sequence

  • Starter Skeleton