The fresh review shows the “192” display collapses to three root categories: 3 unrouted U5 control connections, conflicting GND/18 V fills, and the known U5 footprint pad overlap. I’m correcting the fill-layer configuration and U5 routing first, then I’ll rerun the full review rather than relying on the editor’s aggregate count.
The attempted fixes were reverted because they introduced shorts or 114 airwires, so the board remains in its prior state. Completing this safely requires replacing/reworking U5’s footprint and rebuilding the two internal planes rather than applying another routing patch.
I’ll rebuild the problematic U5 area rather than patching it: replace or correct the defective footprint, rework its local placement/routing, rebuild the internal power planes safely, then iterate DRC until the board is electrically connected and manufacturable.
I identified the required repair path and prepared the full rebuild: correct/replace U5, reconnect and reroute its support network, rebuild the GND and firing-rail planes, then iterate DRC to zero blocking errors.
Execution stopped because no ACUs are available. No additional PCB changes were made in this attempt; the board remains at 3 U5 airwires, 1 plane-fill conflict, and 1 U5 footprint overlap.
Use dummy resistive loads only during initial tests. Never connect live initiators during bring-up.
J1, J2, and J3 are 8P8C/RJ45-style NON-ETHERNET IGNITION OUTPUTS. Never connect them to Ethernet equipment, structured cabling, PoE, switches, routers, computers, or network testers.
J8 is the 8P8C/RJ45-style NON-ETHERNET COBRA INPUT and J10 is COBRA THRU / PASS-THROUGH. J10 must be a direct same-number copy of J8 pins 1–8. Pins 7/8 are fixed positive; pins 1–6 retain selectable return taps through J9. Fit exactly one J9 jumper.
Begin with J6 ARM loop open and the battery supply current-limited. Keep an accessible emergency disconnect in series with J4.
Treat FIRE_RAIL_BATTERY_DEPENDENT_3A as hazardous pulse energy whenever J6 is closed.
Actual rails, protection, and test access
Table
Node
Access/designators
Expected
BAT_RAW
J4-1, F1 input
Applied 15–21 V; J4-2 is GND
BAT_FUSED
F1 output, D1 anode
Input after 5 A fuse F1
BAT_PROTECTED
D1 cathode, TP1, U2/U5 inputs
Battery minus D1 path drop; clamped by D2
3V3
TP2, J7-1
3.3 V logic rail from U2; target 3.20–3.40 V
FIRE_RAIL_BATTERY_DEPENDENT_3A
TP3, U5 outputs, J1/J2/J3 pins 7 and 8
Follows protected battery when enabled; not regulated 18 V; U5 limit nominal 2.98 A from R43=6.04 kΩ
TRIGGER_ISO_N
TP4, U1 PC13
High idle, low while valid COBRA input is present
GLOBAL_FIRE_ENABLE
TP5, U1 PB8, U5 /SHDN, J6-2
Low/disarmed through R44=10 kΩ; PB8 must remain high-impedance
GND
TP6, J7-2, J4-2
Logic/power return
U4 hardware window uses R42=200 kΩ and C12=1 µF for nominal ~100 ms. FIRE_WINDOW_TRIG is U1 PB9; FIRE_WINDOW_Q appears at J6-1. Closing the external ARM loop connects J6-1 to J6-2/GLOBAL_FIRE_ENABLE. Q19, driven by U1 PB11 through R48, clamps MONO_RESET_N low after lockout.
Equipment
Isolated, adjustable 0–25 V bench supply with current-limit readback.
DMM and low-ohm four-wire measurement if available.
Electronic load or non-inductive power resistors with pulse-energy ratings.
Function generator or isolated 18 V pulse fixture for J8. Do not defeat U3 isolation by tying generator ground to board ground unless the test plan explicitly requires it.
ST-LINK and current firmware image.
Dummy channel loads only. Start with 100–330 Ω for logic/sequence observation; use purpose-sized power resistors for controlled current-limit tests.
Pass: stable 3.3 V across input range, logic-only input current 0.3 V or >1 ms at any channel command; TP5 remains low with J6 open; watchdog recovery returns all channels off. Any unexplained gate pulse is a hard fail requiring root cause.
Stage 4 — isolated input qualification
Apply pulses at J8: pins 7/8=COBRA_IN_PLUS; select exactly one return by fitting one J9 shunt at position 1–6, which maps to the same-numbered J8 pin and COBRA_IN_RETURN. Monitor TP4. Verify with an ohmmeter before power that the selected J8 return pin alone reaches COBRA_IN_RETURN, unselected pins remain open, and neither J9 row can connect a return to pins 7/8.
Idle: TP4 must be logic high.
Apply 30 ms nominal 18 V pulse: TP4 should go low for the pulse; no CHx_CMD, PB9 trigger, or sequence advance is allowed.
Repeat at 69 ms: reject.
Apply 100 ms nominal pulse: accept exactly once; CH1 command becomes active and the next released/accepted pulse selects CH2.
Hold the input continuously active for ≥500 ms: exactly one request, never repeated until release.
Test 70 ms boundary with calibrated equipment and characterize tolerance; production threshold must be based on measured timing uncertainty.
Repeat the 100 ms acceptance test for J9 positions 1 through 6, moving the single shunt between tests. Confirm only the same-numbered J8 return pin works in each position and document that multiple jumpers are prohibited.
With power removed, verify continuity J8-1→J10-1 through J8-8→J10-8. Verify every cross-number combination is open (for example J8-1 must not connect to J10-2), proving there is no inversion or remapping. Repeat the pulse tests through J10 and confirm the selected return behavior is identical to J8.
Pass: 30 ms rejected with zero advance; 100 ms accepted exactly once; release required; no channel overlap. Fail: firmware/input filtering investigation required.
Stage 5 — U4 hardware monostable and ARM loop
Keep J6 open. Trigger PB9 through firmware and monitor J6-1 FIRE_WINDOW_Q and TP5.
Verify J6-1 produces one non-retriggered/bounded pulse nominally ~100 ms from U4/R42/C12. Record minimum/maximum across 15, 18.5, 21 V input, temperature corners available, and component tolerance.
With J6 open, verify TP5 remains low and U5 firing rail is disabled regardless of J6-1.
Close J6 only with the supply current limit reduced and no live load. Verify TP5 follows the hardware window and returns low when the window ends.
Force/observe PB11 LOCKOUT_INHIBIT high; Q19 must pull MONO_RESET_N low and prevent any later U4 window.
Pass: J6 open always inhibits U5; J6 closed permits only the bounded U4 window; measured hardware pulse must be ≤110 ms for prototype acceptance and target 100 ms nominal. Fail: do not proceed to load testing.
Stage 6 — firing rail and current limit with resistors
Use a pulse-rated dummy resistor and J6 closed. Start at 15 V with bench current limit 0.25 A.
Verify TP3 is near 0 V outside the U4 window and rises only during an accepted/armed window.
Increase source limit and load stress in controlled steps. Use short pulses only and calculate resistor energy E=V²t/R.
Characterize U5 current limit with a suitable electronic load or resistor bank. R43 predicts 2.98 A nominal; accept 2.7–3.3 A pending TPS26630 tolerance and instrument accuracy. Do not use a bench supply incapable of safely handling pulsed limiting.
Confirm rail voltage follows BAT_PROTECTED minus switch/drop losses over 15–21 V; it is not regulated to 18 V.
Pass: firing rail exists only in armed hardware window; current limit 2.7–3.3 A; no thermal damage; pulse ≤110 ms hardware and ≤100 ms firmware request. Fail: disable firing tests and investigate U5/J6/U4.
Stage 7 — channel sequencing and RJ45 map
Connect one dummy resistor from one return pin to either positive pin 7 or 8. Never short channel returns together.
Issue 18 qualified 100 ms pulses, each separated by release. Verify only the mapped channel conducts, in order, for ≤100 ms requested and ≤110 ms hardware maximum. After CH18, PB10 lockout LED and PB11 inhibit must remain asserted, all MOSFETs off, and subsequent pulses ignored. Power cycle must restore CH1 as next channel with all outputs initially off.
Pass: exact one-hot order 1–18, no skipped/repeated/overlapping channel, permanent lockout after 18 until power cycle. Fail: field use prohibited.
Stage 8 — brownout, faults, and margins
Repeat active and idle interruptions at 15, 18.5, and 21 V, including slow ramp, 1–100 ms dropouts, reset button/SWD reset, and watchdog expiration. Outputs must fail off.
Short each dummy-load output only through a controlled fixture; verify U5 limiting and F1 protection without damaging J1–J3. Do not repeatedly fault contacts.
Open J6 during a request: firing rail must shut down immediately.
Verify a stuck-low input cannot create more than one request without release.
RJ45 contact pulse-current prototype validation
The available TE 1-406541-5 source is a customer drawing. It specifies a 1.5 A continuous/contact rating but provides no short-pulse current curve, so that value is not a demonstrated hard limit for a 100 ms firing pulse. Pins 7 and 8 share positive current, but every channel has one return contact on pins 1–6; U5 permits a nominal 2.98 A.
Test one return contact at the actual 2.98 A current limit for repeated 100 ms pulses. Include worst-case connector/cable aging and ambient temperature. Measure contact-path voltage drop and contact heating during the pulse series, then inspect the connector, PCB jack, mating plug, and cable for damage or degradation. Existing commercial COBRA usage with multiple initiators is relevant field evidence, but it does not automatically qualify this exact connector, PCB jack, mating plug, cable, and current-limiter combination. Record this as a prototype-validation item, not an absolute release blocker.
Bring-up records
Record board serial, firmware hash, instruments/calibration, ambient temperature, supply settings, every rail measurement, pulse widths, current-limit waveform, channel map result, connector temperature/voltage drop, observed failure, and disposition. Two-person review is required before any transition beyond dummy loads.
Non-negotiable safety rules
Actual rails, protection, and test access
Equipment
Stage 1 — unpowered inspection
Stage 2 — logic-only power
Stage 3 — fail-safe startup and programming
Stage 4 — isolated input qualification
Stage 5 — U4 hardware monostable and ARM loop
Stage 6 — firing rail and current limit with resistors