# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** nicobe - **Created:** 3/13/2025 - **Last Updated:** 3/13/2025 - **Visibility:** Public ## Key Components ### IC1 — [INA326EA/2K5](https://www.flux.ai/vasyl/ina326ea2k5~ctt.md) - Manufacturer Part Number: INA326EA/2K5 - Part Type: Integrated Circuit - Manufacturer Name: Texas Instruments - Datasheet URL: https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Fina326 **Pins:** - - [pin 2] - + [pin 3] - ~ [pin 6] - R1 [pin 1] - R1 [pin 8] - R2 [pin 5] - V- [pin 4] - V+ [pin 7] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/nicobe/2-layer-jlcpcb-constraints~x0](https://www.flux.ai/nicobe/2-layer-jlcpcb-constraints~x0).* --- *Generated from [https://www.flux.ai/nicobe/2-layer-jlcpcb-constraints~x0](https://www.flux.ai/nicobe/2-layer-jlcpcb-constraints~x0)*