ESP32-S3 Controller Design
Worked for 29 mins 9 sec
I’m blocked again because the account has no available ACUs, so I can’t continue executing schematic edits right now.
Accomplished in this session:
- Added the core real components: ESP32-S3-WROOM-1-N16R8, TPSM63610 5 V buck, LMR33630 3.3 V buck, TPS7A2033 audio LDO, TPS259474 eFuse, DRV8874, 74LVC2G08, USB-C, ESD, fuses, connectors, MOSFETs, test points, LEDs, ferrite bead, and support passives.
- Wired major power architecture: 12 V battery input, input fuse/reverse MOSFET/TVS/bulk, BAT_PROTECTED distribution, MD10A/TB6600/myRIO branches, TPSM63610 +5V_MAIN, fused +5V_LOGIC/+5V_SERVOS/+5V_MARKER, +3V3_DIGITAL, +3V3_AUDIO, ESP32 power/EN/BOOT, and USB-C native USB D+/D− with CC pull-downs and VBUS sense.
- Used datasheet-backed values for the TPSM63610, LMR33630, TPS7A2033, ESP32-S3 boot/reset, and USB-C sink behavior.
Open items:
- The schematic is not complete yet: microphones, servos, TB6600 MOSFET sinks, myRIO UART, DRV8874/AND-gate marker motor logic, LEDs, and several test points still need final wiring.
- The TPS259474 myRIO eFuse configuration pins need proper individual resistor/cap networks; I had flagged the current placeholder approach for correction.
- Schematic organization/placement and ERC cleanup have not been completed.
- Final fuse values, battery max voltage, motor/servo stall currents, TB6600 resistor values, and myRIO input limits are still TBD.
Suggested next steps once ACUs are available:
- Finish wiring the remaining signal/interface blocks.
- Correct the myRIO eFuse configuration network.
- Organize the schematic into readable functional blocks.
- Run ERC/design review and fix real violations before moving to PCB layout.
Finish and review
Fix eFuse network
Finish signal wiring
Organize schematic
Run ERC review
