Edge13 Schematic Review

Thought for 3 sec

The PCB Placement Pass was already reconciled against the live board; no additional project changes were made this session.

Verified state:

All 134 footprints are placed: 81 top / 53 bottom
J3 USB-C: (27, −32.9) mm, bottom edge
J4 USB-A: (44.72, −21) mm, right edge
J5 USB-B: (−44.5, −21) mm, left edge
BT1: provisional bottom-side placement at (0, 2) mm
J1/J2 remain locked at (±17, 12.5) mm, 90° rotation, preserving the official 34 mm CM5 spacing
Board remains 110 × 75 mm, four copper layers
No reported component-body overlaps or out-of-bounds footprints
No routed traces exist; 285 airwires remain
The 18 pre-existing legacy GND via nodes remain

Remaining issues:

BT1’s 94.6 × 26 mm body conflicts with the fixed CM5/antenna region. Its position cannot be accepted until enclosure and vertical-clearance geometry are resolved.
D3 retains a library/differential-pair warning that must be reviewed before USB routing.
Routing congestion is expected near J1, U5, R17, R18, and TP11.
Connector plug/enclosure clearance has been planned geometrically but still requires enclosure-level validation.

Execution stopped because your ACUs ran out.

Received notification from "PCB Placement Pass" that it finished — picking the work back up.

Thought for 5 sec

flux

The PCB Placement Pass was already fully reconciled against the live board. This is a duplicate completion notification, so no further changes were made.

Placement is complete; remaining unresolved items are the provisional BT1/CM5 mechanical conflict, the D3 USB warning, and enclosure-level connector clearance validation. No routing or schematic changes were performed.

mvillano

stop all work

Thought for 3 sec

flux

Stopped. No further project changes will be made.

Received notification from "PCB Placement Pass" that it finished — picking the work back up.

Thought for 5 sec

flux

This is a duplicate completion notification. The placement pass was already reconciled, and the user subsequently ordered all work stopped. No further inspection, placement, routing, or project changes were performed.

Files

Schematic

Code

Layout

3D View

J3 USB4085 Replacement Verification

Scope status

Table

Requirement	Status	Live evidence
Replace J3 only with GCT USB4085-GF-A	Completed	J3 now instantiates Flux part UID `fcfcfd52-62fa-43f5-81b4-3c79a92084ef`, part version `b5e85569-cc72-43da-b14c-43e033051cef`.
Preserve USB-C service/power nets	Completed	All VBUS, GND, CC, D+/D− mappings are restored; SBU contacts remain intentional no-connects.
Use matched library footprint and model	Completed with library defect noted	Footprint `USB4085-GF-A.kicad_mod`; model `usb4085-gf-a.stp`. Shell stakes 17–20 are incorrectly authored as NPTH in the library footprint, so physical plated shell grounding is not available even though schematic terminals 17–20 are on GND.
Bottom-edge outward placement	Completed	J3 live edge rule lies exactly on board Y = −37.500 mm and reports `faces="down"`.
No new overlap/out-of-bounds/placement keepout violation	Completed	Final placement engine: 0 overlaps, 0 out-of-bounds. Existing 13 fixed/BT1 keepout reports are unchanged from before this replacement.
Board/stackup unchanged	Completed	110 × 75 mm, custom four-layer, total thickness 1.60 mm.
Routing unchanged	Completed	No routeSegment nodes; virtual via count remains 18. No routing tool or copper mutation was used.

J3 live readback

Designator: J3
Manufacturer: GCT (Global Connector Technology)
MPN: USB4085-GF-A
LCSC/JLCPCB part: C7095263
Part UID: fcfcfd52-62fa-43f5-81b4-3c79a92084ef
Position: X = +27.0000 mm, Y = −28.7011 mm
Rotation: 0°
Layer: Top
Component body bounds: approximately X = 21.69…32.31 mm, Y = −34.24…−23.16 mm
Footprint: USB4085-GF-A.kicad_mod
3D model: usb4085-gf-a.stp
Footprint edge rule: direction 180°, inferred offset 8.799 mm; rendered edge line at Y = −37.500 mm, facing down/outward.
Datasheet suitability: top-mount, side-entry USB 2.0 Type-C receptacle; 2.10 mm shell-stake length is compatible with the unchanged 1.60 mm board.

Full terminal mapping

The library symbol uses numbered terminals. The mapping is derived from the published part’s ordered 16-contact pattern and the GCT component-side recommended PCB layout.

Table

J3 terminal	USB-C contact	Function	Net
1	A1	GND	`GND`
2	A4	VBUS	`USB_C_VBUS_RAW`
3	A5	CC1	`USB_C_CC1`
4	A6	DP1	`SERVICE_USB_DP`
5	A7	DN1	`SERVICE_USB_DN`
6	A8	SBU1	Intentional no-connect
7	A9	VBUS	`USB_C_VBUS_RAW`
8	A12	GND	`GND`
9	B12	GND	`GND`
10	B9	VBUS	`USB_C_VBUS_RAW`
11	B8	SBU2	Intentional no-connect
12	B7	DN2	`SERVICE_USB_DN`
13	B6	DP2	`SERVICE_USB_DP`
14	B5	CC2	`USB_C_CC2`
15	B4	VBUS	`USB_C_VBUS_RAW`
16	B1	GND	`GND`
17	Shell stake	Shield/retention	`GND` in schematic
18	Shell stake	Shield/retention	`GND` in schematic
19	Shell stake	Shield/retention	`GND` in schematic
20	Shell stake	Shield/retention	`GND` in schematic

Live net membership confirms:

USB_C_VBUS_RAW: J3 pins 2, 7, 10, 15.
GND: J3 pins 1, 8, 9, 16, 17, 18, 19, 20.
USB_C_CC1: J3 pin 3.
USB_C_CC2: J3 pin 14.
SERVICE_USB_DP: J3 pins 4, 13.
SERVICE_USB_DN: J3 pins 5, 12.
No-connects: J3 pins 6, 11.

Pad count and footprint quality

Live J3 pad nodes: 20 total.
Pads 1–16: sixteen 0.4064 mm drilled through-hole contact pins on 0.85 mm pitch, arranged as two rows.
Pads 17–20: four shell/retention stake holes.

Blocking library-footprint limitation

The source footprint payload defines shell stake pads 17–20 as np_thru_hole ovals rather than plated through-hole solder pads. This conflicts with the GCT recommended PCB layout’s solder-area intent and the exact project requirement that all four shell stakes be grounded. The schematic terminals are connected to GND, but the current library footprint provides no plated annular copper for a physical shell-to-GND connection. No footprint edits were made because the task explicitly required the existing library footprint/model. A Flux part-quality report was filed against https://www.flux.ai/adrian95/usb4085-gf-a.

Nearby placements changed

Table

Part	Previous position	Final position	Layer	Reason
D1	(+27.0, −27.0) mm	(+30.0, −25.3) mm	Top	Clear the deeper connector body and align the USB ESD array behind the new contact field.
C2	(+30.5, −27.0) mm	(+34.0, −25.5) mm	Top	Clear J3/D1 while retaining local raw-VBUS bulk capacitance.
D4	(+35.0, −34.5) mm	(+19.0, −31.0) mm	Top	Clear the new J3 body and its routing keepout while remaining in the USB-C raw-VBUS region.
C37	(+33.0, −28.0) mm	(+41.0, −30.0) mm	Bottom	Clear J3 and remain near U2’s eFuse timing pin.
TP17	(+33.0, −25.5) mm	(+36.0, −27.0) mm	Top	Resolve the local conflict created by moving C2; remains accessible.

No other component placement was changed.

Verification results

Placement checks

Component-body overlaps caused by this change: 0.
Components outside board caused by this change: 0.
Placement keepout violations caused by this change: 0.
J3 edge placement: success; line at Y = −37.500 mm, mating face down/outward.
Existing raw keepout count remains 13, consisting of the previously documented BT1 versus CM5 all-layer-body exclusions and fixed J1/J2/CM5-hole self-intersections. These were not changed.

Board-check diagnostic

The final check-board run reports 60 pre-routing warnings. Relevant to this change:

J3 pins 1, 8, 9 and 16 are reported inside edge-connector keepouts; the routing checker explicitly states those keepouts will be ignored. This is an edge-connector routing-model condition, not a component-body placement violation.
One ROUTING_UNROUTABLE_DIFFERENTIAL_PAIR_PINS warning remains on D1 for the service USB pair. Moving D1 directly behind J3 did not clear it. Both J3 and D1 expose duplicated flow-through pads on each USB data net; the board checker treats one set as independent differential-pair endpoints. Resolving this requires explicit routing or a part/router model change, both outside this component-replacement-only scope.
The prior D3 duplicate-pad warnings and Q1/Q6 same-net multi-pad warnings remain unrelated and unchanged.

Integrity confirmation

Board outline: unchanged, 110 × 75 mm.
Stackup: unchanged, 1.60 mm four-layer.
Net names and net properties: unchanged.
All non-J3 schematic connectivity: unchanged.
Routing state: unchanged; 0 route segments, 18 existing virtual stitching vias.
No traces, vias, pours, board rules, or unrelated component properties were authored.

Scope status
J3 live readback
Full terminal mapping
Pad count and footprint quality
Blocking library-footprint limitation
Nearby placements changed
Verification results
Placement checks
Board-check diagnostic
Integrity confirmation