Refine this doc
Ask about this doc
Project Specification — USB-C WiFi BLE T-RH Sensor Node
Requirements
  • Consumer low-power environmental node.
  • USB-C receptacle, 5 V default sink input.
  • Plan for USB-C sources advertising 0.5 A to 3 A; the design must not assume 3 A is always available in firmware/use.
  • Digital temperature / relative humidity sensor.
  • Ultra-low-power Wi-Fi + Bluetooth dual-radio MCU: 2.4 GHz 802.11 b/g/n and BLE 5.x.
  • Input path must include reverse-current/reverse-polarity, overvoltage, undervoltage lockout, and overcurrent protection.
Selected architecture
  • USB-C USB 2.0 receptacle: GCT USB4105-GF-A.
  • USB-C sink detection: independent 5.1 kΩ Rd pulldowns on CC1 and CC2.
  • USB data: routed to ESP32-C3 native USB Serial/JTAG through USBLC6-2SC6 ESD protection.
  • Input protection: TPS25210LRPWR eFuse, 2.7 V to 5.7 V operating input, 4 A switch, reverse current blocking, input reverse-polarity protection, overvoltage clamp, adjustable UVLO and current limit.
  • 3.3 V conversion: AP63203WU-7 fixed 3.3 V synchronous buck regulator, 2 A output capability.
  • MCU/radio: ESP32-C3-WROOM-02-N4 module, 3.0 V to 3.6 V supply, Wi-Fi 802.11 b/g/n and Bluetooth 5.
  • Sensor: Sensirion SHT41-AD1B-R2 I2C T/RH sensor, VDD 1.08 V to 3.6 V, address 0x44.
Datasheet-grounded design notes
  • ESP32-C3 requires stable 3.3 V rail capable of at least 0.5 A. Peak Wi-Fi TX current from datasheet is 345 mA at 802.11b 1 Mbps, 20.5 dBm.
  • ESP32-C3 EN must not float. Use 10 kΩ pull-up and 1 µF RC delay/filter per Espressif peripheral schematic guidance.
  • ESP32-C3 boot/download: GPIO9 weak-pull-up default = SPI boot; pull GPIO9 low with BOOT button for joint download boot. GPIO2 is recommended pulled up.
  • ESP32-C3 USB Serial/JTAG uses GPIO18 = USB_D- and GPIO19 = USB_D+.
  • SHT4x typical application: SDA/SCL pull-ups to VDD, 100 nF capacitor from VDD to VSS close to sensor.
  • AP63203 fixed 3.3 V typical application: 10 µF input capacitor, 3.9 µH inductor, 2 × 22 µF output capacitors, 100 nF bootstrap capacitor.
  • TPS25210L USB 5 V protection design example: UVLO 4 V using 470 kΩ / 205 kΩ divider, OVCSEL open for 5.7 V clamp, RILM 953 Ω for 3.5 A current limit, 1 nF dVdt capacitor, 2.2 nF ITIMER capacitor, 10 µF output capacitor.
Power budget

Table

RailLoadTypicalPeak
3.3 VESP32-C3 Wi-Fi/BLE module80–150 mA active estimate345 mA Wi-Fi TX peak; supply sized for >=500 mA per datasheet
3.3 VSHT41 sensor=2.7 A saturation current, low DCR preferred.
Open layout constraints for next phase
  • Place ESP32-C3-WROOM-02 antenna at board edge with antenna keepout clear of copper, traces, components, and enclosure metal.
  • Place SHT41 away from heat sources: buck regulator, eFuse, ESP32 module, and status LED.
  • Keep AP63203 input cap, inductor, bootstrap cap, and output caps tightly looped.
  • Put USB ESD protection close to the USB-C receptacle.

  • Requirements

  • Selected architecture

  • Datasheet-grounded design notes

  • Power budget

  • Protection sizing

  • Open layout constraints for next phase