I’ll turn this concept into a grounded project specification first, then verify whether the named off-the-shelf parts can actually support a 2 mm³ battery-less audio/RF node before attempting a schematic. I’ll rename the blank project, capture the requirements, and do a feasibility/power-component check against available part data.

I renamed the project and captured the concept in Project Specification. I also completed a datasheet-grounded feasibility check in Feasibility and Power Analysis.

Conclusion: the exact 2 mm cube off-the-shelf design should not proceed to schematic as stated—the microphone and EFR32-class SoC packages alone exceed the volume, and the 01005 buffer capacitor is orders of magnitude too small for RF/audio burst energy. Recommended next step is to choose a revised target: larger proof-of-concept PCB, true custom bare-die/SiP research package, or reduced-function NFC-style node.

I’ll design a practical proof-of-concept schematic around the same RF SoC, PDM mic, Schottky rectifier, and GRM02 buffer concept. I’ll size the power path first, add the components and support circuitry, wire the schematic, then run review and document the firmware/power notes.

Designed the larger proof-of-concept schematic around the EFR32MG22, SPK0641HT4H-1 mic, SMS7621 rectifier bridge, GRM02 benchmark capacitor, larger reservoir cap, AP2112K 3.3 V rail, SMA RF test port, coil input, SWD header, reset, decoupling, and RF match.

I documented the implementation in Proof-of-Concept Design Notes and added firmware bring-up guidance in Firmware Starter. Schematic connectivity is complete; remaining review issues are expected layout airwires and generic-part MPNs to resolve before fabrication. Next step is PCB layout setup and placement—ready when you want me to proceed.