Creating MTB GPS Device
- Complete wiring: charger BAT→LDO VIN; unify 3V3; ground the sensor header.
- Net naming: set GPIO_SEL; confirm GPIO_UP/DOWN; label SDA/SCL/INTs.
- I2C: wire 4.7k pull-ups to SDA/SCL and 3V3.
- Cleanup: replace GND portals with Ground symbols; add enclosure/USB sealing notes.
- Run ERC/DRC and availability.
Started implementing a plan
#Goal
- Finalize the BLE-only MTB GPS schematic to include an external SMA antenna, LiPo power/charging circuitry, three active‑low buttons (GPIO_UP, GPIO_DOWN, and GPIO_SEL), and an I2C sensor header. The schematic should have complete wiring, proper net naming and symbols, and pass ERC/DRC checks, so it is ready for PCB layout.
#Implementation plan
1. **Wiring Completion**
1. Connect the charger BAT output to the LDO U6 (XC6220B331MR) VIN pin to feed the 3V3 rail.
2. Ensure that all parts of the 3V3 rail are properly tied together, including connections to the ESP32-C6 and components as needed.
3. Tie the sensor header (J3, 0022232071) ground to the main Ground, ensuring proper grounding of I2C and other sensor essentials.
2. **Net Naming and Signal Integrity**
1. Rename the existing SW_SEL net to GPIO_SEL to confirm consistent naming for active‑low buttons.
2. Verify and label the GPIO_UP and GPIO_DOWN nets accordingly.
3. Label the I2C lines (SDA and SCL) and any interrupt (INT) lines on the sensor header.
3. **I2C Pull-ups Configuration**
1. Wire the 4.7k resistors (R1 and R2) as pull-ups on the SDA and SCL lines to 3V3.
4. **Component and Symbol Cleanup**
1. Replace GND portals with standard Ground symbols throughout the schematic for clarity.
2. Add enclosure and vent notes, and incorporate USB sealing notes relating to the USB-C connector (J1, MEM2067-02-180-00-A).
5. **Review and Validation**
1. Run ERC/DRC checks to ensure that there are no electrical or connection errors.
2. Verify parts availability and cross-check component datasheets as needed.
#Success criteria
- The LiPo charger BAT is successfully connected to the LDO U6 VIN with proper 3V3 rail stability.
- All active‑low buttons (GPIO_UP, GPIO_DOWN, and renamed GPIO_SEL) are correctly connected and named.
- I2C lines have correct 4.7k pull-ups connected to 3V3, and sensor header ground is properly tied to system ground.
- GND symbols have been standardized and enclosure/USB notes are clearly indicated on the schematic.
- The completed schematic passes ERC/DRC checks and is ready for the PCB layout phase.
- Edge I/O: place J1 USB‑C and J2 SMA at board edges; position SW_UP, SW_DOWN, SW_SEL along an accessible side.
- RF: short 50 Ω route from U1 to J2; place D1, C9, L2 tight to connector; add RF keepouts/via fence.
- Power/GND: place U6 near ESP32 3V3 entry; put 0603 decouplers at IC pins; solid GND plane with stitching, separate RF returns from high‑current paths (knowledge base guidance).
- Sensors: place J3 accessible; route SDA/SCL and INTs away from RF; keep pull‑ups close.
- Rules/DRC: set 50 Ω width per stackup, label critical nets, run DRC/ERC (Flux review runs continuously).
