Custom Mainboard Design for Forensic Device
Thought for 9 sec
You’re looking at the main project, not the connector part project.
In your screenshot:
- Left side = chat/Copilot panel
- Right side = component library/search/properties area
- You are not inside the cloned Amphenol connector part editor
Open this part project directly:
That should take you to the imported connector part by itself.
Then:
- Click Schematic at the top.
- Click one of the small terminal symbols on the connector.
- The properties panel should appear on the right side.
- Look for fields like:
- Pin Number
- Pin Name
- Terminal / Pad
But honestly, don’t fight the UI too much.
Easier path
Since the part already exists at:
If you can find a way to rename the terminals there, do it. If not, send Flux support this:
I need help renaming the terminals onmkgemmell/20021121-00040t4lfto createOlimex_GPIO1, while preserving terminal numbers 1–40 and the existing footprint pads 1–40.
The exact terminal list is the one we already built.
Verify and support
Verify Amphenol parts
Draft support request
Create mapping docs
Plan next schematic
Refine this doc
Ask about this doc
USB2 Prototype Architecture Update
Status: Superseded. The project has pivoted to the Olimex iMX8MP-SOM-4GB-IND USB3 write-block intake-controller architecture. Do not continue routing or repairing the STM32H753 + USB3300 path unless the project explicitly returns to the lower-cost USB2-only prototype.
Decision
The write-block front end was previously a USB2-only STM32H753 prototype to reduce cost and complexity. This is no longer the active path.
What Changed
- Removed the STM32MP257 Linux/MPU front end.
- Removed external DDR4, STPMIC25 PMIC, eMMC, QSPI NOR, and the related support passives.
- Added U2 = STM32H753ZIT6 as the write-block supervisor/controller.
- Kept U8 = Raspberry Pi Compute Module 5 as the main compute/UI/scanning processor.
- Kept J3 USB-A evidence connector, but the first prototype path is USB2 only.
- Added J8 = 10-pin SWD header for STM32 programming/debug.
- Added Y1 = 25 MHz HSE crystal with C62/C63 load capacitors for the STM32H753 clock.
- Replaced the earlier USB3343-CP ULPI PHY with U18 = USB3300-EZK because the compact USB3343 QFN could not be escaped by the available router.
- Replaced the 26 MHz USB3343 oscillator with U19 = DSC1001DI1-024.0000T, because USB3300 requires a 24 MHz reference on XI.
Current USB Evidence Path
- J3 USB2 D+/D- route through U9 ESD protection to U18 USB3300 DP/DM.
- U18 connects the physical USB2 bus to the STM32H753 through the ULPI bus.
- J3 VBUS is switched by U12 BD2222G current-limited high-side switch.
- STM32H753 controls evidence VBUS enable and reads the overcurrent/fault signal.
- STM32H753 communicates control/status to the CM5 over a provisional UART link.
USB3300 Support Added
- U18 VDD3.3 pins and REG_EN are tied to the 3.3 V logic rail.
- U18 VDD1.8 / VDDA1.8 are tied to the local 1.8 V regulator-output bypass net.
- U18 RBIAS uses the existing 8.06 kΩ 1% resistor to ground.
- U18 ID is strapped to ground for host-side behavior.
- U18 VBUS sense uses the existing series resistor from USB_EVIDENCE_VBUS.
- U19 provides the required 24 MHz clock into U18 XI; U18 XO is left floating for active-clock mode.
ULPI Implementation Status
- U19 = DSC1001DI1-024.0000T provides the 24 MHz active reference clock into U18 XI; U18 XO remains intentionally unconnected for active-clock mode.
- U18 ULPI bus is wired to STM32H753: DATA0 PA3, DATA1 PB0, DATA2 PB1, DATA3 PB10, DATA4 PB11, DATA5 PB12, DATA6 PB13, DATA7 PB5, CLKOUT PA5, STP PC0, DIR PC2_C, NXT PC3_C.
- KSZ switch management was moved off the ULPI pins to PE2/PE5/PE6/PE4.
- Evidence USB VBUS enable/fault moved to PG0/PG1.
- CM5 UART moved to PD5/PD6.
Open ULPI Items
- Verify STM32H753 alternate-function setup in firmware for the selected ULPI, SPI, UART, and GPIO pins.
- During layout, route the ULPI bus short and grouped, with the 60 MHz CLKOUT trace treated as the timing reference.
- Validate USB3300 24 MHz active-clock configuration during bring-up.
- Current routing blocker: the available router still cannot escape the U18 QFN pads, even for local VDD3.3 decoupling and XI clock routes. Manual via/bottom-layer escape or a different routing workflow is required.
Important Limitation
STM32H753 does not implement USB3 SuperSpeed write-blocking. This prototype is for lower-cost USB2 high-speed write-block gatekeeping and BadUSB/descriptor checks. A future USB3 design will need dedicated USB3-capable bridge/switch hardware or a return to an MPU/SoC front end.
Follow-up Work
- Source or create a correct 26 MHz reference part for USB3343.
- Reassign conflicting STM32 GPIO/SPI/control pins and wire the ULPI bus.
- Clean up obsolete project notes that still reference STM32MP257 as the active write-block front end.
- Route and validate the simplified layout.
Decision
What Changed
Current USB Evidence Path
USB3300 Support Added
ULPI Implementation Status
Open ULPI Items
Important Limitation
Follow-up Work
