Custom USB Switch Design
Worked for 7 mins 4 sec
The schematic is electrically back in a clean, verified state: all intended USB, power, MCU, CC, and control nets are intact, and ERC shows no open errors or warnings. I rolled back the unsafe cleanup attempt and preserved the working design rather than risking hidden connectivity damage.
Open items:
- The remaining messy visual labels are platform-generated portal labels that did not persist when renamed through the available schematic edit path.
Suggested next steps:
- Proceed to PCB layout from the verified netlist.
- Add status LEDs before layout if desired.
- If visual schematic cleanup is still important, use the schematic editor manually to relabel/group portals, since the automated rename path did not stick.
Yes, move on to PCB layout from the verified netlist.
Thought for 6 sec
I’ll move into PCB layout: set up an appropriate USB 2.0 board/stackup, place the connectors/mux/protection/power/control parts, route the critical USB pairs, then run layout checks.
Worked for 40 mins 41 sec
Processing was stopped.
Here's a summary of what I was working on:
Troubleshooting PCB layout issues
I need to address the USB_A pins, which might be blocked due to the connector placement being too far out of bounds. The current board dimensions might need resizing, perhaps to 75x50 or even 80x55, to avoid this issue. I also have to consider the existing routes; they might get messy if I change the layout or need to delete dangling connections after rerouting. I’ll definitely check the history to revert to a workable state before the auto-route.
Check USB routing
Inspect 3V3 clearance
Widen power traces
Optimize placement
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Board Bring-Up Plan — USB 2.0 Host Switch
Prerequisites
- Equipment: multimeter, current-limited 5 V bench supply or protected USB-C 5 V source, oscilloscope if available, AVR ISP programmer, sacrificial USB2 host/hub for first tests.
- Firmware: see the firmware starter project file.
- Safety: do not connect expensive laptops or the DAC during first power-on. Do not connect J3 to a PC, charger, power bank, or other source/DFP.
1. Visual Inspection
- Confirm U1 TS3USB30EDGSR, U2 ATTINY85V-10SU, U3 MIC5205-3.3YM5, U4 TPD3S014, J1/J2/J3/J4, D1/D2, SW1, J5, R1-R13, and C1-C7 are populated.
- Check USB-C connector soldering for bridges, especially D+/D−, CC, VBUS, and GND pins.
- Confirm C7 is the intended 150 uF capacitor footprint and orientation if a polarized capacitor is used.
- Confirm no solder bridges on U1 VSSOP pins.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Tolerance | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|---|
| 5V_EXT | J4 USB-C power input | 5.0 V | ±5% | J4 VBUS, U3 IN, U4 IN | Start 50-100 mA | Board powers without overcurrent |
| 3V3 | U3 MIC5205 OUT | 3.3 V | ±3% initial target | U3 OUT, U1 VCC, U2 VCC | Included in 5V_EXT limit | 3.2-3.4 V |
| VBUS_HUB | U4 OUT, MCU-enabled | 0 V before firmware; ~5 V after firmware enables | ±5% | U4 OUT, J3 VBUS | 500 mA continuous target | Off during reset, on after firmware |
| HOST_A_VBUS | J1 host | ~5 V only when Host A connected | Host-dependent | J1 VBUS, D1 VBUS | No board load intended | Isolated from 5V_EXT/HOST_B_VBUS |
| HOST_B_VBUS | J2 host | ~5 V only when Host B connected | Host-dependent | J2 VBUS, D2 VBUS | No board load intended | Isolated from 5V_EXT/HOST_A_VBUS |
Procedure:
- With no cables attached, measure resistance from 5V_EXT, 3V3, VBUS_HUB, HOST_A_VBUS, and HOST_B_VBUS to GND.
- Confirm HOST_A_VBUS is not shorted to HOST_B_VBUS, 5V_EXT, or VBUS_HUB.
- Power J4 from a current-limited 5 V source at 50-100 mA.
- Confirm 5V_EXT is ~5 V and 3V3 is ~3.3 V.
- Before firmware runs, confirm U1 ~OE is high and U4 EN is low if possible.
- After programming firmware, confirm VBUS_HUB turns on only when firmware enables U4.
- Load-test VBUS_HUB with a resistor/e-load before attaching the real hub. Test 100 mA first, then 500 mA.
3. Critical Signal Verification
Table
| Signal | Net Name | Expected State | Measure At | Notes |
|---|---|---|---|---|
| USB mux select | MUX_SEL_MOSI | LOW for Host A, HIGH for Host B | U1 S / U2 PB0 | Shared with AVR ISP MOSI |
| USB mux disconnect | MUX_OE_MISO | HIGH = disconnected, LOW = connected | U1 ~OE / U2 PB1 | R11 pulls high during reset |
| Hub VBUS enable | HUB_VBUS_EN | LOW during reset, HIGH when hub VBUS enabled | U4 EN / U2 PB4 | R13 pulls low during reset |
| Reset | AVR_RESET | Pulled HIGH to 3V3 | U2 RESET / J5 RST | Pulled up by R9 |
| Switch input | SWITCH_REQUEST | HIGH idle, LOW pressed | U2 PB3 / SW1 | Pulled up by R10 |
Procedure:
- Program the firmware with J1/J2/J3 disconnected.
- Confirm U1 ~OE transitions high during switching and low after the guard delay.
- Confirm U1 S changes only while U1 ~OE is high.
- Confirm U4 EN can be toggled by firmware and VBUS_HUB follows it.
4. Connector and Interface Tests
Table
| Connector | Type | Pins to Verify | Test Method |
|---|---|---|---|
| J1 | USB-C Host A UFP-facing | CC1/CC2 Rd, D+/D−, isolated VBUS, GND | Resistance and continuity; then sacrificial host enumeration |
| J2 | USB-C Host B UFP-facing | CC1/CC2 Rd, D+/D−, isolated VBUS, GND | Resistance and continuity; then sacrificial host enumeration |
| J3 | USB-C hub DFP-facing | CC1/CC2 Rp, VBUS_HUB, D+/D−, GND | Verify with hub only; never connect to a source/host |
| J4 | USB-C power input | CC1/CC2 Rd, VBUS, GND | Verify 5 V input and CC pull-downs |
| J5 | AVR ISP | MISO, MOSI, SCK, RST, VCC, GND | Programmer target-detect and flash test |
Procedure:
- With power off, verify CC resistors: R1-R6 are 5.1 kΩ to GND; R7/R8 are 56 kΩ to 5V_EXT.
- Verify J1/J2 host VBUS rails remain isolated from each other and from 5V_EXT.
- Use short, known-good USB2-capable cables for first data tests.
- Test Host A path first with one sacrificial host and a simple self-powered hub.
- Test Host B path second.
- Test switching with keyboard/mouse first, then DAC, microphone, and webcam.
5. Programming and Debug Interface
Table
| Interface | Signals | Connector | Tool |
|---|---|---|---|
| AVR ISP | MOSI/PB0, MISO/PB1, SCK/PB2, RESET/PB5, 3V3, GND | J5 | USBtinyISP, USBasp, or equivalent AVR ISP |
Procedure:
- Disconnect J1, J2, and J3 before programming.
- Connect programmer to J5.
- Confirm programmer sees the ATtiny85 target at 3.3 V.
- Flash the firmware starter image.
- After flashing, verify SW1 causes U1 ~OE and U1 S to sequence correctly.
6. Functional Validation
Table
| Test | Components Involved | Input | Expected Output | Pass Criteria |
|---|---|---|---|---|
| Initial Host A connection | U1, U2, J1, J3 | Power on with hub connected to J3 and host on J1 | Hub enumerates on Host A | Host sees hub and simple USB device |
| Host B connection | U1, U2, J2, J3 | Toggle SW1 | Hub enumerates on Host B | Host B sees hub and devices |
| Break-before-make | U1, U2 | Press SW1 | ~OE high before S changes | No momentary short/cross-connect |
| Hub VBUS control | U2, U4, J3 | Firmware toggles HUB_VBUS_EN | VBUS_HUB turns off/on | VBUS_HUB follows U4 EN without 5V_EXT brownout |
| DAC transition | U1, U2, U4, hub, DAC | Toggle between hosts | DAC re-enumerates high-speed/working audio | No low-speed distorted-audio failure |
7. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Tolerance | Instrument |
|---|---|---|---|---|
| 5V_EXT | U3 IN / U4 IN | 5.0 V | ±5% | DMM |
| 3V3 | U3 OUT / U2 VCC | 3.3 V | ±3% target | DMM |
| CC Rd | J1/J2/J4 CC pins to GND | 5.1 kΩ | ±1% resistor tolerance | DMM |
| CC Rp | J3 CC pins to 5V_EXT | 56 kΩ | ±1% resistor tolerance | DMM |
| VBUS_HUB off | U4 OUT before firmware enable | 0 V | near 0 V | DMM |
| VBUS_HUB on | U4 OUT after firmware enable | ~5.0 V | ±5% | DMM |
| USB D+/D− pair | J1/J2/J3 to U1 | Continuity, no shorts | No D+/D− short | DMM; scope optional |
Known Prototype Caveats
- J3 is intended only for the self-powered hub upstream/UFP connection. Do not plug J3 into a computer, charger, or power bank.
- J1 and J2 both present USB-C sink Rd resistors; connected hosts may source VBUS even when not selected.
- The first revision does not include a full USB-C port controller or attach detection.
- TPD3S014 is a 500 mA USB switch, but fault current can be higher than 500 mA before current limiting/thermal protection.
- USB 2.0 high-speed performance depends strongly on 4-layer layout, short differential routing, and correct ESD placement.
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power Rails | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| Connectors | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Functional Validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for extended testing / [ ] Requires rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug Interface
6. Functional Validation
7. Expected Measurements Reference
Known Prototype Caveats
Pass/Fail Summary
