Reference Design Review
Source
- Upstream project: https://github.com/pms67/HadesFCS
- License: BSD 3-Clause; derivative work must preserve the required copyright and license notices.
- User-supplied manufacturing BOM reviewed on 2026-08-13.
What HadesFCS Provides
HadesFCS is a strong flight-controller and navigation-computer reference, but it is not documented as an integrated four-channel ESC/PDB. The source includes KiCad hardware, firmware, FreeRTOS-based control software, simulator and ground-control tooling.
The supplied BOM confirms these major blocks:
- STM32H753VIT6 primary flight-control MCU.
- STM32F405RGT6 navigation MCU.
- BMI088 inertial sensor.
- IIS2MDCTR magnetometer.
- MPRLS0025PA pressure sensor and TMP100 temperature sensor.
- MAX-8Q GNSS module and SMA RF connector.
- W25N01 serial NAND, two 24CW1280 EEPROMs, PCA9685 I/O/PWM expander, and INA219 current monitor.
- MIC26903-based switching regulator and LD39200 3.3 V LDO.
- Two 10-pin 1.27 mm SWD headers and multiple Micro-USB connectors.
Blocks Worth Reusing
- Dual-MCU functional partition and independent SWD access.
- Sensor and nonvolatile-memory functional set.
- External GNSS, RC input, UART, I2C, ADC, and PWM connectivity concepts.
- Input voltage/current monitoring concept.
- Firmware and test infrastructure where licensing and pin mapping remain compatible.
Blocks Requiring Redesign or Review
- Four ESC power stages, motor connectors, gate drivers, MOSFETs, shunts, bulk capacitance, transient suppression, and thermal design are new.
- The PDB must be sized only after battery and motor-current requirements are fixed.
- Micro-USB should be reconsidered in favor of USB-C for data/bench power, without a flight-pack charging path.
- MAX-8Q and other older components require lifecycle and availability review.
- INA219 is suitable for modest bus monitoring but may not be the best device for fast high-current propulsion measurements.
- PCA9685 is not the preferred path for high-rate DShot; H753 timers/DMA should drive the ESC interface directly.
- Existing power conversion must be recalculated for the expanded avionics loads and battery range.
Signal- and Power-Integrity Learning Targets
- Controlled 90-ohm USB differential routing using the fabricator's real 8-layer stackup.
- 50-ohm RF routing and antenna-launch practice.
- Solid reference planes and return-via placement at every signal-layer transition.
- Separation of IMU/analog regions from high di/dt ESC loops.
- Gate-drive loop minimization, switch-node containment, and Kelvin current sensing.
- Plane impedance, decoupling hierarchy, anti-resonance awareness, and rail isolation.
- Inter-processor SPI timing, source damping, and length/return-path discipline.
- High-current copper, via-array, connector, thermal, and transient validation.
Recommended Architecture Direction
Use the HadesFCS schematic as a reference baseline rather than a literal copy. First recreate and modernize the compute/sensor/debug core, then add one fully validated ESC channel and replicate it four times only after electrical and thermal review. Keep RF module-based in revision A so the project teaches controlled RF routing without making radio certification and discrete matching the dominant risk.
Critical Inputs Still Required
- Flight pack: 4S or 6S.
- Continuous and peak motor current per channel.
- Target ESC control architecture: BLHeli_32-compatible dedicated ESC MCUs, a custom STM32G0/C0 per channel, or direct experimental control.
- RF standard/module: ExpressLRS, external telemetry radio, Wi-Fi/BLE, or another link.
- Target board dimensions and mounting pattern.