• Advanced PCB design and embedded-systems learning platform.
• Initial prototype, not flight-certified or safety-certified hardware.
• Multirotor operation is assumed for the integrated four-channel ESC/PDB.

• Run real-time flight control on an STM32H753VIT6.
• Run navigation, supervision, or redundancy tasks on an STM32F405RGT6.
• Acquire inertial, magnetic, pressure, GPS, temperature, voltage, and current data.
• Drive four brushless motors through integrated three-phase ESC stages.
• Distribute raw flight-pack power and generate clean avionics rails.
• Support USB device connectivity and independent SWD access for both MCUs.
• Provide RF/telemetry through a segregated module or connector interface.

• STM32H753VIT6 primary flight-control computer.
• STM32F405RGT6 secondary navigation/safety computer, retained from HadesFCS.
• HadesFCS sensor baseline: BMI088 IMU, IIS2MDC magnetometer, MPRLS0025 pressure sensor, TMP100 temperature sensor, and MAX-8Q-class GNSS as a reference set subject to lifecycle review.
• External nonvolatile storage and I/O expansion based on the useful HadesFCS blocks.
• Four independent ESC channels and central PDB.
• USB 2.0 interfaces; no onboard flight-pack charging.
• Separate SWD headers for both processors.

Diagram

• STM32H753VIT6 in LQFP-100.
• Dedicated clocking, reset/boot controls, local decoupling, analog filtering, USB protection, and SWD.

• STM32F405RGT6 in LQFP-64, matching the upstream HadesFCS BOM.
• Used for navigation, supervisory functions, sensor partitioning, or redundancy.
• Independent SWD and reset access.

• Reuse HadesFCS architecture where technically appropriate, but revalidate every device for availability and current datasheet guidance.
• Physically isolate inertial sensors from ESC switching nodes, inductors, motor phase copper, and board flex.

• Four three-phase brushless motor stages.
• Raw battery distribution, bulk capacitance, transient suppression, voltage/current sensing, gate-drive supplies, and thermal monitoring.
• Exact topology and parts remain dependent on battery cell count and motor current.

• Prefer a certified RF module or connectorized radio for the first revision.
• Maintain antenna keepout and a controlled 50-ohm path where an RF connector is used.

• USB is for data, configuration, and bench power only; it will not charge the flight pack.
• Independent SWD connectors for both MCUs. Full JTAG is optional only if pin budget and board area justify it.

• Flight battery input and four motor phase outputs.
• USB 2.0 device interface.
• Two SWD headers.
• GNSS, telemetry/RF, RC input, and expansion UART/I2C connectors.
• Inter-processor high-speed SPI plus interrupt/health lines is the preferred starting architecture.
• DShot-capable timer outputs from the H753 to each ESC controller or gate-driver control path.

• No onboard flight-pack charging.
• USB must not back-power the propulsion bus.
• Avionics must tolerate battery transients and ESC-induced conducted noise.
• Final battery range and current ratings are not yet confirmed.

• LiPo cell count and operating voltage range.
• Continuous and peak motor current per channel.
• Desired regulated auxiliary outputs for receiver, GPS, servos, or payloads.

• Eight copper layers.
• Controlled-impedance fabrication with the selected board house's actual stackup.
• Heavy outer copper may be required for propulsion current; impedance calculations must use the final copper thickness and dielectric geometry.
• Prototype assembly may require a mixed strategy because large MOSFETs, current shunts, connectors, and fine-pitch sensors impose different soldering needs.

• Independent boot/reset/debug access for each MCU.
• Hardware watchdog and inter-processor heartbeat/fault signaling.
• DMA-capable SPI for inter-processor communications and sensor acquisition.
• Timer/DMA resources reserved for DShot.
• Sensor data-ready interrupts routed to suitable MCU interrupt pins.

• Proposed starting stackup intent: L1 signal/components, L2 solid GND, L3 high-speed/low-noise signal, L4 power, L5 power, L6 solid GND, L7 low-speed/control signal, L8 signal/components/high-current copper.
• Final layer usage must be reconciled with ESC power loops; uninterrupted ground references are mandatory under USB, clocks, SPI, and RF.
• Partition the board into propulsion, power-conversion, digital-compute, sensor, and RF zones.
• Keep the IMU near the mechanical center and away from high-current switching loops.

• Use HadesFCS as an architectural reference rather than blindly cloning it.
• Retain STM32H753VIT6 and STM32F405RGT6 direction from the supplied BOM.
• Exclude USB flight-pack charging.
• Use an 8-layer controlled-impedance board as an explicit learning objective.
• Treat integrated ESC/PDB design as a new subsystem requiring its own power, thermal, and EMI validation.

• Four-motor multirotor platform.
• USB 2.0 High Speed capability is desired on the H753 where practical.
• RF will initially be module-based or connectorized rather than a discrete radio transceiver and antenna match.
• Exact board dimensions, battery voltage, current rating, ESC firmware architecture, and RF standard remain open.

• Initial specification created from the HadesFCS repository and supplied BOM.
• USB charging removed from scope.
• Added integrated four-channel ESC/PDB, RF/telemetry, 8-layer signal-integrity focus, and dual-MCU architecture.