Audit target: ESP32-S3-DevKitC-1-N8R2 installed in carrier sockets J14/J15, with J9/J10 as unpopulated one-to-one breakouts.
Result: the live schematic and PCB are already consistent with Espressif’s authoritative component-side/top-view mapping for component-side-up insertion with the DevKit USB end facing the carrier’s right-hand board edge. No socket net reassignment, rotation, copper deletion, or rerouting was required. Blindly changing J14/J9 pins 21 and 22 to GND would be incorrect for the present physical orientation.
Espressif’s component-side view has J3 on the left and J1 on the right, with pin numbers running from the antenna end (pin 1) toward the USB end (pin 22). The carrier rotates this arrangement 90° counter-clockwise: antenna end is toward carrier X−/left, USB end is toward carrier X+/right, J1 becomes the upper row, and J3 becomes the lower row. A bottom-side view would visually reverse this relationship and must not be used for socket mapping.
Official header pinout
J1 — carrier J14 and breakout J9
Table
Pin
Official function
Live net
1
3V3
ESP_3V3_BREAKOUT
2
3V3
ESP_3V3_BREAKOUT
3
RST/EN
ESP_RST
4
GPIO4
LORA_TXEN_GPIO4
5
GPIO5
LORA_RXEN_GPIO5
6
GPIO6
LORA_DIO2_GPIO6
7
GPIO7
LORA_DIO1_GPIO7
8
GPIO15
ESP_GPIO15
9
GPIO16
ESP_GPIO16
10
GPIO17
GPS_TXD_TO_ESP_RX_GPIO17
11
GPIO18
GPS_RXD_FROM_ESP_TX_GPIO18
12
GPIO8
LORA_BUSY_GPIO8
13
GPIO3
ESP_GPIO3
14
GPIO46
ESP_GPIO46
15
GPIO9
LORA_RESET_GPIO9
16
GPIO10
LORA_CS_GPIO10
17
GPIO11
LORA_MOSI_GPIO11
18
GPIO12
LORA_SCK_GPIO12
19
GPIO13
LORA_MISO_GPIO13
20
GPIO14
ESP_GPIO14
21
5V
5V
22
GND
GND
J3 — carrier J15 and breakout J10
Table
Pin
Official function
Live net
1
GND
GND
2
U0TXD/GPIO43
ESP_U0TX_GPIO43
3
U0RXD/GPIO44
ESP_U0RX_GPIO44
4
GPIO1
ESP_GPIO1
5
GPIO2
ESP_GPIO2
6
GPIO42
ESP_GPIO42
7
GPIO41
ESP_GPIO41
8
GPIO40
ESP_GPIO40
9
GPIO39
ESP_GPIO39
10
GPIO38
ESP_GPIO38
11
GPIO37
ESP_GPIO37
12
GPIO36
ESP_GPIO36
13
GPIO35
ESP_GPIO35
14
GPIO0
ESP_GPIO0
15
GPIO45
ESP_GPIO45
16
GPIO48
ESP_GPIO48
17
GPIO47
ESP_GPIO47
18
GPIO21
GPS_PPS_GPIO21
19
GPIO20/USB D+
ESP_USB_D+_GPIO20
20
GPIO19/USB D−
ESP_USB_D-_GPIO19
21
GND
GND
22
GND
GND
Physical readback
All four headers are on the top side.
Table
Ref
Function
Center (mm)
Rotation
Physical pin-1 end
Physical pin-22 end
J14
DevKit J1 socket, upper row
(4.635, 19.200)
0°
X−/left, antenna end
X+/right, USB end
J15
DevKit J3 socket, lower row
(4.635, −6.200)
0°
X−/left, antenna end
X+/right, USB end
J9
J14/J1 breakout
(4.635, 24.2998)
180°
X−/left
X+/right
J10
J15/J3 breakout
(4.635, −11.300)
180°
X−/left
X+/right
The 180° rotations on J9/J10 compensate for the breakout footprint’s native origin/orientation; readback of pad coordinates and copper confirms pin N remains vertically aligned with socket pin N. Therefore the breakouts are one-to-one, not reversed.
J14-to-J15 row spacing is 25.40 mm, matching the Espressif mechanical arrangement. Pin pitch is 2.54 mm. The DevKit is inserted from the carrier top with its components visible, antenna end toward the left, and USB connectors toward the right-hand board edge/open space.
User GND concern
J14:21 = 5V, not GND. This is correct because J14 is physically the official J1 row in the selected component-side-up, USB-right orientation.
J14:22 = GND.
J9:21 = 5V, not GND. J9 is the one-to-one breakout for J14/J1.
J9:22 = GND.
The positions that are both GND are J15:21/J15:22 and their one-to-one breakout J10:21/J10:22, because J15/J10 implement official J3.
Changing J14/J9 pins 21 and 22 both to GND would remove the intended protected 5 V feed to the DevKit and would contradict Espressif’s official J1 pinout.
Power-architecture check
DevKit 5 V enters at J14:21/J9:21 on net 5V, downstream of the existing protection path.
DevKit 3V3 pins J14:1 and J14:2 are on isolated net ESP_3V3_BREAKOUT; they are not tied to the carrier 3.3 V rail.
GPS/LoRa remain powered from the carrier 3.3 V architecture. No 3V3 backfeed path was introduced.
Validation readback
Schematic mapping: all 44 socket positions match Espressif J1/J3 pin numbers and functions; J9 mirrors J14 pin-for-pin and J10 mirrors J15 pin-for-pin.
ERC: no matching open warnings/errors were returned by the selected electrical checks at 2026-08-13 08:06 UTC.
Socket-specific changes: none were necessary, so this audit introduced zero new ERC/DRC issues and invalidated no copper.
Current board routing state is not globally complete: 18 pre-existing airwires remain, including ESP32 endpoint nets such as GPIO35, GPIO2, GPIO12, GPIO10, GPIO9, GPIO8, GPIO4, GPIO18, GPIO7, GPIO11, GPIO13, GPIO5, GPIO6, GPIO21, GPIO17, and 5V, plus one unrelated rail connection. Two pre-existing dangling traces are reported (e902bc4b…, f14572c9…).
Current DRC also reports 44 pre-existing invalid-layer trace errors because the declared stackup is standard-1-layer while existing copper includes bottom-layer traces. These issues predate this no-change audit and were not modified because they are outside the focused socket-orientation correction scope.