SHT45 Probe Design


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Reading PCB-B Release Check's report…
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Steering SHT45 Probe Design
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Received notification from "SHT45 Probe Design" that it finished — picking the work back up.
The preliminary two-board design is now complete and independently verified.
  • PCB-A: 35 × 4 mm, four-layer 1.30 mm preliminary stackup, clean sensor tongue with exactly four 0.15 mm traces, 0 airwires and clean ERC/DRC.
  • PCB-B: standalone TRACE-M8-4P-CARRIER-V1, 13 mm diameter, 1.60 mm two-layer stackup, verified Binder geometry and mapping, fully routed with clean ERC/DRC.
  • All parent documentation is synchronized in Project Specification and Sources/Open Issues.
  • No manufacturing-release files were generated.
Open approval items
  • CM confirmation of the thin four-layer PCB-A stackup; 1.30 mm exceeds the preferred 0.6 mm.
  • PCB-B annular-ring and finished-thickness approval.
  • Enclosure, seal, connector load-path, solder-access and strain-relief validation.
  • First-article electrical, I²C, harness and pull testing.
Next steps
  1. Send both boards to a CM for DFM/stackup review.
  2. Finalize and fit-check the enclosure.
  3. Incorporate CM feedback and run the release review.
  4. Generate manufacturing files only after explicit approval.
Prepare CM review
Design enclosure
Evaluate thinner PCB-A
Plan prototype testing

J1
J2
J3
D1
R3
Resistance
4.7 kΩ
R1
Resistance
33 Ω
R2
Resistance
33 Ω
R4
Resistance
4.7 kΩ
C2
Capacitance
4.7 µF
D2
TP2
U1
TP4
TP1
TP3
C1
Capacitance
100 nF
Design Sources and Open Issues
Verification status
This is a preliminary approval-gate record, not a manufacturing release. No Gerbers, drill files, IPC netlists, or production CPL were generated.
The datasheet evidence service returned the requested technical text but did not finish immutable citation indexing. Therefore, exact technical facts below are identified as official-source extracted / citation pending rather than represented as fully citation-resolved.
Authoritative sources consulted
Confirmed electrical facts used in the design
  • SHT45 package pins: 1 SDA, 2 SCL, 3 VDD, 4 VSS; the exposed central die area is not used as a PCB pad.
  • SHT45 fixed address for the selected A-code variant: 0x44; serial-number command: 0x89.
  • Current SHT4x application circuit uses 100 nF VDD-to-VSS local decoupling.
  • Highest nominal 200 mW heater mode is budgeted at up to 100 mA maximum; heater is disabled in normal operation.
  • Sensirion explicitly requires no copper under the package except the four pin pads and advises against soldering/exposing copper under the central die area.
  • TPD2E2U06DCKR: two passive ESD channels plus GND, 5.5 V working range, 1.5 pF typical channel capacitance, 10 nA maximum leakage, SC-70-3.
  • PESD3V3U1UL,315: unidirectional 3.3 V standoff device; cathode to +3V3 and anode to GND.
Binder successor finding
Finding: Binder identifies 86 6119 1100 00004 as the current order number and lists 09 3391 81 04 as the alternative/old number. This is an order-number transition, but Binder also warns that technical deviations may exist. Therefore:
  • Treat 86 6119 1100 00004 as the current successor ordering reference.
  • The newly supplied controlled package pairs current-order metadata for 86 6119 1100 00004 with the vendor file 09-3391-81-04.STP; this resolves the production footprint/model geometry for the supplied revision.
  • The schematic and BOM use the current number and retain the legacy CAD filename for traceability.
  • Any future Binder revision still requires change-control comparison because Binder's order-number notice allows technical deviations.
Connector geometry — controlled files received
The supplied controlled PDF and CAD ZIP resolve the connector type, rear-mount direction, PCB hole pattern, pin numbering, body/hex envelope, panel cutout and vendor STEP availability. The PDF's Conductor layout and Contact arrangement (Plug-in side) panels carry identical pin orientation: 2 upper-left, 4 upper-right, 1 lower-left and 3 lower-right. The asymmetrical rows register directly to the STEP tail coordinates; no drawing-view mirror is applied to the footprint.
The vendor STEP uses X as the connector axis, with the tail/PCB side at negative X and mating/thread side at positive X. The four Ø0.6 mm tails are at controlled footprint coordinates pin 1 (−1.700, −0.500), pin 2 (−1.075, +1.450), pin 3 (+1.700, −0.500), pin 4 (+1.075, +1.450) mm in the shown component-side view. Finished holes are Ø1.3 mm.
Resolved panel data: M8×1, Ø8.1 mm through-hole, 0.5×45° chamfer, 2.0–3.5 mm mounting-wall range and 1 N·m panel fastening torque. The connector is inserted from inside/rear and secured outside/front.
Remaining connector uncertainties are narrower: no explicit PCB-thickness requirement, no ±/general tolerance block, and no specified seal material/hardness/compression or replacement part number. The black seal-like ring and body grooves are depicted, and the product is potted/IP67, but those facts do not define a serviceable seal.
PCB-B diameter decision
  • Final preliminary carrier: 13.0 mm circular board in the standalone TRACE-M8-4P-CARRIER-V1 project.
  • Four Ø1.8 mm connector pads around Ø1.3 mm finished holes give a 0.25 mm nominal radial annular ring. On the 13.0 mm disk, worst connector-pad copper clearance is 3.795 mm to the physical edge; the maximum 11.547 mm connector envelope has 0.7265 mm radial clearance to the physical edge.
  • A four-pad 2.4 mm-pitch harness interface is included. Protection and test functions remain on PCB-A.
  • Active PCB-B layout read-back is 1.60 mm. Binder does not specify PCB thickness, so finished-thickness convention/tolerance remains subject to CM/assembly confirmation.
  • Controlled Binder mapping and vendor STEP registration are verified in the linked board project.
  • PCB-B verification returned 0 ERC/DRC findings, 0 airwires and 0 dangling traces.
  • PCB-B controlled geometry and derivation.
PCB-A routing status — verified clean repair
  • Authorized TP2 repair completed: TP2 is at board-centered X = 2.35 mm, Y = -1.10 mm, Bottom, 0°. No other component was moved and the custom 35 mm × 4.0 mm blade outline, SHT45 tip, thermal neck/tongue, airflow region and harness interface were unchanged.
  • TP2's Ø1.0 mm copper pad overlaps the existing GND through-via annulus centered at approximately (1.65, -1.20) mm. Center separation is approximately 0.707 mm versus 0.800 mm combined pad/via radius, while the 0.3 mm drill hole remains approximately 0.707 mm from the pogo target center and is not beneath it.
  • Obsolete custom copper polygons TP2 direct GND fill tongue and TP2 local GND fill bridge remain disabled in the active layout.
  • PCB-A uses the Flux custom-standard-4-layer stackup with Top, Mid-Layer 1, Mid-Layer 2 and Bottom all configured as signal copper, plus 0.6/0.3 mm L1–L4 through vias. This removes the former continuous inner GND/power planes beneath the thermally isolated tongue.
  • Four explicit layer-specific keepouts cover board-centered x = -17.5 to -8.4 mm, y = -2.0 to +2.0 mm. Inner-layer zones prohibit all copper; Top/Bottom zones prohibit fills, polygons and vias while permitting U1/C1 pads and routed traces.
  • The sensor tongue/neck now carries only four 0.15 mm Top traces: SDA_SENSOR, GND, +3V3 and SCL_SENSOR. C1 remains as the permitted local 100 nF VDD-to-VSS connection. All vias and layer transitions are rearward of x = -8.4 mm; the former SDA via beneath U1 and +3V3 neck via are disabled.
  • Fresh parent-project review at 2026-09-03T18:17:44Z reports 0 open ERC/DRC findings. Routing-state read-back reports 0 airwires and 0 dangling traces.
  • Auto-router feasibility preflight reports only expected pin-inside-keepout warnings for U1/C1 because the selector-specific tongue zones intentionally contain allowed pads/traces; the completed routing was authored and verified directly.
  • The active stackup reports 1.30 mm total thickness. This materially exceeds the preferred 0.6 mm blade construction and is therefore a manufacturing/mechanical approval item; no fabrication files were exported.
Linked PCB-B project status
PCB-A remains the active layout in this parent project. PCB-B now exists as the separate, editable TRACE-M8-4P-CARRIER-V1 project, rather than as an artifact-only representation. The linked project contains the 13.0 mm circular board, 1.60 mm thickness read-back, connector and harness footprints, verified Binder model/mapping, completed routing and clean ERC/DRC evidence.
Remaining approval blockers
  1. PCB-A CM approval of a thin production four-layer stackup, thickness tolerance, panelisation/pallet/depanel process, 0402/SOD-882 capability, 0.125/0.15 mm features and 0.8 mm harness-pad drill; otherwise explicit mechanical approval of the 1.30 mm preliminary stackup.
  2. PCB-B CM approval of the 1.60 mm finished-thickness convention/tolerance and engineering-selected Ø1.8 mm pad OD / 0.25 mm radial annular ring.
  3. Connector/seal tolerance, material, hardness/compression and replacement/service data.
  4. Enclosure/load-path/fit approval, including connector capture, axial stops, solder-tool access and PCB/harness clearances.
  5. Connector and harness solder wetting/access/inspection criteria.
  6. Enclosure-based strain relief and qualified conductor/assembly pull-test criteria.
  7. First-article mating-face electrical checks plus SHT45 I2C/CRC/serial and exact 0.5 m, 100 kHz production-cordset validation.
  8. Production sourcing and material-compatibility approval for connector, enclosure, wire insulation, strain relief, coating/potting and packaging.
  9. Final human release authorization before Gerbers, drill files, IPC test netlists, BOM/CPL release packages or other manufacturing exports are generated.
  • Verification status

  • Authoritative sources consulted

  • Confirmed electrical facts used in the design

  • Binder successor finding

  • Connector geometry — controlled files received

  • PCB-B diameter decision

  • PCB-A routing status — verified clean repair

  • Linked PCB-B project status

  • Remaining approval blockers