USB Analyzer Design
Thought for 9 sec
Voy a ordenar el esquemático por bloques y luego configurar el PCB inicial: tamaño de placa, stackup/reglas base, anchos para 2 A y restricciones USB.
Worked for 24 sec
No puedo continuar ejecutando cambios ahora porque no hay ACUs disponibles; por eso no puedo ordenar el esquemático ni aplicar tamaño/reglas de PCB en esta sesión.
Hecho en esta sesión:
- Inicié el plan de trabajo para ordenar esquemático y preparar layout.
- Cargué la guía técnica necesaria para ordenamiento de esquemático, tamaño de PCB, stackup y reglas USB/2 A.
Pendiente cuando haya ACUs:
- Ordenar el esquemático por bloques: USB/protección, switch/shunt/INA226, RP2040, OLED/UI y firmware header.
- Leer densidad de layout y definir tamaño de PCB; mi punto de partida recomendado será 4 capas por USB 2.0 y corriente de 2 A.
- Configurar reglas: VBUS de 2 A con pistas/cobre ancho, USB D+/D- como par diferencial ~90 Ω, GND interno sólido y power plane interno.
- Verificar ERC/DRC después de los cambios.
Conseguir ACUs
Ordenar manualmente
Reglas concretas
Tamaño inicial
Refine this doc
Ask about this doc
Power Budget and Shunt Sizing
USB Power Analyzer V1
Key decision
Use a 20 mΩ current-sense shunt, 1%, ≥1 W, preferably 2512 or dedicated current-sense footprint with Kelvin routing.
At the V1 target current:
- Current:
2 A - Shunt resistance:
0.02 Ω - Voltage drop:
V = I × R = 2 A × 0.02 Ω = 0.04 V = 40 mV - Power dissipation:
P = I² × R = 2² × 0.02 = 0.08 W
A 1 W part gives very large thermal margin. The earlier 0.1 Ω idea would drop 200 mV and dissipate 0.4 W at 2 A, so it is worse for USB voltage delivered to the DUT.
TPS2559 current-limit setting
The original TPS2553 was rejected for the 2 A V1 target because its recommended continuous output current is below the requirement. V1 uses TPS2559DRCR instead.
For TPS2559DRCR, use:
RILIM = 49.9 kΩ, 1%- Datasheet table: approximately 2.215 A minimum, 2.36 A typical, 2.46 A maximum current limit
This allows a real 2 A load to operate without nuisance limiting while still protecting against faults above the V1 target.
3.3 V rail estimate
The RP2040 Stamp provides a 3.3 V rail from its onboard regulator. Estimated peak logic/UI load:
Table
| Load | Estimated peak |
|---|---|
| RP2040 Stamp logic | 100 mA |
| OLED SSD1306 module | 20 mA |
| INA226 | <1 mA |
| 3 status LEDs at ~2 mA each | 6 mA |
| Buzzer/transducer driver | 5 mA |
| Pull-ups/buttons | <1 mA |
| Total peak estimate | ~132 mA |
This is within the RP2040 Stamp 3.3 V output rating reported in its datasheet excerpt: 500 mA max.
USB input current expectation
At full load:
- DUT output target:
2.0 A - Logic/UI overhead: approximately
0.15 Afrom 5 V input including regulator losses and margin - Expected input current at full load: approximately
2.15 A
The selected PTC is 1812L300MR, approximately 3 A hold and ~6 A trip, providing margin for the 2 A DUT load plus analyzer electronics.
Important source limitation
A standard PC USB-A port may not legally provide 2 A. V1 should be tested at 2 A from a USB power source or charger rated for at least 5 V / 2.5 A, not from a normal USB 2.0/3.0 data port unless current capability is known.
Layout requirements
- Route shunt as true Kelvin sense to INA226
Vin+andVin-. - Keep high-current VBUS path wide from input connector → PTC → TPS2559 → shunt → output connector.
- Place INA226 close to the shunt.
- Place TPS2559 input/output capacitors close to the IC.
USB Power Analyzer V1
Key decision
TPS2559 current-limit setting
3.3 V rail estimate
USB input current expectation
Important source limitation
Layout requirements
