Capacitive Touch LED Control System Schematic
Thought for 8 sec
nets {
net 3V3 = U1:VOUT, U1:TAB(VOUT), C4:P1, C15:P1, R2:P1, C12:P1, U2:VCC, IC1:3V3, C11:P1, U2:LED, C9:P1, C10:P1, C2:P1, R13:P2, C3:P1, C14:P1, C7:P1, U5:VDD, J1:Pin_1, R1:P2, C6:P1, R3:P1, C13:P1, C8:P1, DS1:VDD;
net BOOT = R13:P1, IC1:IO0;
net TFT_RST = U2:RESET, IC1:IO16;
net TOUCH_RST = IC1:IO5, J1:Pin_6;
net GND = Q3:E, DS1 VSS_2 - U5 VSS:GND, R14 P2 - C15 P2:GND, C15:P2, IC1 GND_11 - U2 GND:GND, U2:GND, C12 P2 - C13 P2:GND, C13:P2, U5:A0, U5:A1, U5:A2, GND:GND, C10:P2, R8:P2, IC1:GND_11, IC1:GND_10, IC1:GND_9, IC1:GND_8, IC1:GND_7, IC1:GND_6, IC1:GND_5, IC1:GND_4, IC1:GND_3, IC1:GND_2, DS1 VSS - DS1 LED(-):GND, DS1:LED(-), R14:P2, U4:2, C1:P2, C3:P2, C7:P2, C12:P2, U5:VSS, C11:P2, J1:Pin_2, C9:P2, DS1:R/W, C2:P2, C6:P2, Q1:E, IC1:GND_1, R9:P2, R7:P2, U1:GND, C4:P2, Q2:E, C8:P2, DS1:VSS, C14:P2;
net Net 2 = IC1:EN, R1:P1;
net I2C_SDA = J1:Pin_3, U5:SDA, R2:P2, IC1:IO8;
net TFT_DC = U2:D/C, IC1:IO15;
net NC_TXD0 = IC1:TXD0;
net NC_TFT_TOUCH_DO = U2:T_DO;
net NC_TFT_TOUCH_DIN = U2:T_DIN;
net NC_IO37 = IC1:IO37;
net TFT_CS = IC1:IO14, U2:CS;
net LED1_CTRL = IC1:IO17, R4:P1;
net SPI_SCK = U2:SCK, IC1:IO13;
net NC_IO47 = IC1:IO47;
net TOUCH_INT = J1:Pin_5, IC1:IO4;
net I2C_SCL = U5:SCL, IC1:IO9, J1:Pin_4, R3:P2;
net NC_IO40 = IC1:IO40;
net SPI_MOSI = IC1:IO12, U2:MOSI;
net NC_IO42 = IC1:IO42;
net NC_IO36 = IC1:IO36;
net NC_IO1 = IC1:IO1;
net NC_IO3 = IC1:IO3;
net NC_IO41 = IC1:IO41;
net NC_IO2 = IC1:IO2;
net NC_TFT_TOUCH_CLK = U2:T_CLK;
net NC_TFT_SD_SCK = U2:SD_SCK;
net NC_IO39 = IC1:IO39;
net NC_IO19 = IC1:IO19;
net TOUCH4 = IC1:IO7;
net NC_IO45 = IC1:IO45;
net NC_IO38 = IC1:IO38;
net NC_IO20 = IC1:IO20;
net NC_IO46 = IC1:IO46;
net LED2_CTRL = R5:P1, IC1:IO18;
net NC_IO35 = IC1:IO35;
net NC_TFT_TOUCH_CS = U2:T_CS;
net NC_IO48 = IC1:IO48;
net NC_TFT_TOUCH_IRQ = U2:T_IRQ;
net NC_IO10 = IC1:IO10;
net LED3_CTRL = R6:P1, IC1:IO21;
net NC_TFT_SD_MOSI = U2:SD_MOSI;
net NC_TFT_SD_CS = U2:SD_CS;
net NC_IO11 = IC1:IO11;
net NC_TFT_SD_MISO = U2:SD_MISO;
net NC_TFT_MISO = U2:MISO;
net TOUCH3 = IC1:IO6;
net NC_RXD0 = IC1:RXD0;
}
Thought for 5 sec
- Set IC1's No Connect Pins to "IO1, IO2, IO3, IO10, IO11, IO19, IO20, IO35, IO36, IO37, IO38, IO39, IO40, IO41, IO42, IO45, IO46, IO47, IO48, RXD0, TXD0"
- Set U2's No Connect Pins to "T_IRQ, T_DO, T_DIN, T_CS, T_CLK, MISO, SD_CS, SD_MOSI, SD_MISO, SD_SCK"
Task completed.
0:48
Checking 6 design areas.
Thought for 4 sec
Work done
- Audited the NC-designated pins on IC1 and U2 against the live schematic state
- Confirmed all NC-designated pins are isolated onto dedicated
NC_*nets and are not tied to active power, SPI, I2C, touch, or LED-control nets - Explicitly documented the no-connect pin lists on IC1 and U2 using component properties
- Re-ran schematic checks and verified there are no no-connect, floating-pin, missing-power, pin-conflict, single-pin-net, or undriven-net ERC errors
Success criteria review
- ✅ Every true NC-designated pin is explicitly documented as no-connect on IC1 and U2
- ✅ Accidental connections of NC pins to active nets are not present; NC pins are isolated on dedicated
NC_*nets - ✅ Active functionality was preserved: power, SPI, I2C, touch header, and the three LED channels were unchanged
- ✅ Schematic validation is clean after the update
Next steps
If you want, I can also do a documentation pass to convert the remaining anonymous net
Net 2 on IC1 into a clearer name such as EN for readability.Fix NC pin isolation
Check only changed nets
Protect LED channels
