Raspberry Pi CM5 Carrier Board Design

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I created the initial high-level CM5 carrier architecture and block diagram in SitePulse CM5 Carrier Board Project Specification, and renamed the project to SitePulse CM5 Carrier Board.
Key decisions captured:
  • CM5-centered carrier with protected 9–60 V input target and high-current 5 V buck rail.
  • Separate kernel I²C, Predator bit-banged I²C, SPI CAN, relay GPIO, debug UART, ADC/sensor, and expansion resources.
  • Recommended CAN direction: MCP2518FD or MCP2515 with rugged transceiver, ESD, and selectable 120 Ω termination.
  • Four protected engine-control outputs instead of bare GPIO/MOSFET outputs.
  • 4-layer compact board, roughly 100 mm × 80 mm starting point, with power/relay connectors separated from CAN/sensor/debug I/O.
Before I build the actual schematic, the main items to confirm are relay output type, CAN isolation requirement, maximum input surge/load-dump requirement, connector preference, and enclosure mounting dimensions.
Low-side relay outputs
Isolated CAN option
Wide input protection
Screw terminal connectors
Board outline choice
L

lwilkinson

answers:
Relay output type: 3–4 channels of optically isolated high-side drivers (or relay + opto), minimum 5–8A per channel. For engine start, kill, and fuel pump control.
CAN isolation: Yes — use an isolated CAN transceiver (e.g. ADM3053 or equivalent) for noise immunity near the engine.
Input surge / load-dump: Design for 12–60V nominal input with protection against 80–100V transients + reverse polarity protection.
Connector preference: Pluggable screw terminals or rugged M12-style for external signals and CAN. Anderson/XT-style or larger terminals for main power. Prioritize field serviceability.
Enclosure mounting: 4-corner M3 mounting holes with vibration isolation. Keep connectors along edges where possible. Target compact size that fits inside SendCutSend IP65 enclosure with reasonable component height.

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Schematic

Layout

3D View

Schematic Implementation Plan
Status
Draft block-level schematic capture plan ready for user review before detailed pin-by-pin wiring. This file records selected parts, schematic grouping, power-budget assumptions, and staged capture order.
Locked Requirements
  • Main processor: Raspberry Pi Compute Module 5 only.
  • Input: 12 V to 60 V nominal battery input.
  • Protection: reverse polarity plus 80 V to 100 V transient/load-dump tolerance.
  • Main rail: 5V_SYS target at least 6 A to 7 A continuous for CM5 and peripherals.
  • Logic rail: 3V3_LOGIC derived from 5V_SYS.
  • CAN: MCP2518FD preferred, isolated CAN transceiver, jumper-selectable 120 ohm termination, ESD protection.
  • Relay/load outputs: 4 channels, optically isolated or protected high-side, 5 A to 8 A capability each.
  • ADC: ADS1115 on kernel I2C-1.
  • I2C: Preserve kernel I2C-1 on GPIO2/GPIO3 and keep Predator sniffer on separate GPIOs.
  • Board target: about 160 mm to 180 mm by 110 mm to 125 mm inside a 207.0 mm by 171.5 mm by 38.6 mm enclosure.
Functional Schematic Groups
Diagram



  
    
  
  
    
  



































"Power Input and Protection"
"VIN_PROT"
"LM5146-Q1 node_5V Buck\nor LTC3895 Alternate"
"5V_SYS"
"CM5 Power Pins"
"AP63203 3.3V Buck"
"3V3_LOGIC"
"CM5 Connectors J1 J2"
"MCP2518FD CAN FD Controller"
"ADM3053 Isolated CAN\nor ISO1042 Option"
"CAN Connector"
"4x TPS1HTC30-Q1 High-Side Channels"
"Engine Control Connector"
"I2C1 GPIO2 GPIO3"
"ADS1115 ADC"
"I2C Expansion"
"Predator Bit-Banged I2C Sniffer"
"UART Debug Status LEDs Test Points"
Selected Parts and Rationale
Power Input and Protection
  • Main input connector: field-serviceable high-current connector or large pluggable terminal. Exact connector footprint to be finalized with enclosure wiring plan.
  • Surge stopper: LT4363IMS-2 class high-voltage surge-stopper/hot-swap controller using external MOSFET. Library part found: LT4363IMS-2#PBF.
  • Reverse polarity: use ideal-diode / N-MOSFET style reverse protection or integrate with the surge stopper front end. LM74610-Q1 remains an alternate for dedicated reverse polarity control.
  • Transient protection: automotive/load-dump TVS such as SM8S/SMCJ family selected after clamp target is finalized. Protection goal is survival through 80 V to 100 V transients while protecting downstream converters.
  • EMI filtering: input common-mode choke or differential LC filter plus bulk capacitance before the 5 V buck.
  • Datasheet check: LT4363 supports 4 V to 80 V operation, withstands surges over 100 V with VCC clamp, and supports reverse-input protection to -60 V. The datasheet shows automotive surge-stopper circuits using external MOSFETs, VCC clamp TVS, 0.1 uF bypass, and current-limit sense resistor. For schematic capture, design the front end as VIN_RAW -> fuse -> TVS/clamp -> reverse/surge MOSFET stage -> EMI filter -> VIN_PROT.
Preliminary Power Budget for 5V_SYS
  • 5V_SYS design target: 7 A continuous for CM5 plus peripherals.
  • Output power at 5 V, 7 A: 35 W.
  • Worst-case nominal input current at 12 V with 90 percent buck efficiency: about 3.24 A, before input-protection losses.
  • At 60 V nominal with 90 percent efficiency: about 0.65 A.
  • Input connector, fuse, reverse-protection MOSFET, surge MOSFET, inductor, and copper must be sized for the 12 V worst-case current plus margin and transient thermal stress.
  • Relay/load currents are separate from 5V_SYS: four 8 A channels could impose up to 32 A on the field-power path if all are used at full load. That current must not flow through the CM5 regulator path.
5 V Main Buck
  • Preferred controller: LM5146-Q1, library part LM5146QRGYRQ1.
  • Reason: 5.5 V to 100 V input synchronous buck controller, suitable for 12 V/24 V/48 V systems and 100 V transient-capable front end. External MOSFETs allow sizing for 6 A to 7 A continuous 5 V output.
  • Schematic note: use the TI datasheet/evaluation design equations to size MOSFETs, inductor, compensation, feedback network, current sense, bootstrap, and input/output capacitors.
  • Alternate found in library: LTC3895IFE#TRPBF, a 150 V low-IQ synchronous step-down controller. Use as a robust alternate if LM5146-Q1 availability, footprint, or modeling is unfavorable. LTC3895 is especially attractive when the 100 V transient requirement needs extra controller headroom.
3.3 V Logic Rail
  • Preferred part: AP63203WU-7 fixed 3.3 V, 2 A synchronous buck.
  • Reason: Derives 3V3_LOGIC efficiently from 5V_SYS with margin for CAN controller, ADC, pullups, LEDs, and support logic.
  • Datasheet support parts: 3.9 uH inductor, 10 uF input capacitor, 2 x 22 uF output capacitors, 100 nF bootstrap capacitor.
  • Library part confirmed: AP63203WU-7. Use a buck instead of a small LDO to keep 3.3 V thermals comfortable if expansion and LEDs grow.
CM5 Support
  • CM5 electrical interface: two 100-pin Hirose DF40C-100DS-0.4V connectors. Library part found: DF40C-100DS-0.4V(58).
  • Need two connector instances for CM5 mating.
  • Include 5V_SYS bulk capacitance near CM5 connector and distributed decoupling.
  • Include RUN/reset, boot mode access, UART debug, and test points.
  • CM5 pin mapping must be verified against the official CM5 datasheet/reference design before detailed wiring.
  • Note: use two connector instances, with exact CM5 connector orientation, mounting height, and keepout copied from the official CM5 reference design before layout.
CAN Bus
  • CAN controller: MCP2518FDT-H/SL, SPI CAN FD controller.
  • Reason: modern CAN FD-capable controller with Linux support path, SPI interface, INT, optional INT0/INT1 GPIO, external oscillator.
  • MCP2518FD support: 0.1 uF VDD decoupling, 20 MHz or 40 MHz crystal/oscillator with load capacitors as selected from the crystal datasheet, SPI mode 0/0 or 1/1, active-low INT, and SPI SCK not exceeding the datasheet timing limit.
  • Preferred isolated transceiver for first schematic pass: ADM3053BRWZ because it includes signal isolation and an integrated isolated DC/DC converter. This avoids a separate isolated CAN supply during early schematic capture.
  • ADM3053 support from datasheet: VIO = 3.0 V to 5.5 V, VCC = 4.5 V to 5.5 V, VIO decoupling 0.1 uF plus 0.01 uF, VCC decoupling 0.1 uF plus 10 uF, VISOOUT tied externally to VISOIN through the recommended ferrite/decoupling network, RS tied to isolated GND for full speed or resistor-controlled for slope control, NC/VREF left unconnected.
  • ISO1042 remains the alternate if we decide to use a separate isolated DC/DC supply for CAN.
  • CAN termination: jumper-selectable 120 ohm across CAN_H/CAN_L; split termination can be used if EMI testing calls for it.
  • CAN protection: CAN bus ESD/TVS array on isolated field side.
Relay / Engine Control
  • Preferred high-side switch: TPS1HTC30-Q1, one per channel, four total.
  • Reason: automotive smart high-side switch, 6 V to 60 V operating range, 30 mOhm typical RON, adjustable 2 A to 16 A current limit, diagnostics, integrated inductive clamp, 3.3 V logic compatible.
  • Isolation: add optocoupler/digital isolator control stage per channel or grouped channel isolation between CM5 logic and field high-side inputs. Because TPS1HTC30 inputs are low-current logic pins, isolating EN/DIAG/LATCH control is practical.
  • Channel names: ENGINE_START, ENGINE_KILL, FUEL_PUMP, SPARE.
  • Datasheet support: RPROT on MCU/control I/O, FAULT pullups, SNS resistor/filter if diagnostics are used, ILIM set resistor or direct-to-GND choice for current-limit behavior, input and output EMI/transient capacitors.
  • Datasheet check: TPS1HTC30-Q1 has EN, DIAG_EN, FAULT open-drain, LATCH, SNS, ILIM, VS, and VOUT pins. EN/logic thresholds support 3.3 V control. Internal current limit defaults to about 8 A when ILIM is open and 16 A when ILIM is grounded; an external RILIM in the datasheet's recommended range can set a custom limit. TI recommends series protection resistors on MCU I/O and provides inductive-load clamp guidance.
I2C and Sensors
  • ADS1115IDGSR ADC on I2C1.
  • Reason: 16-bit, 4 single-ended or 2 differential inputs, simple I2C interface, useful for fuel level, temperature, current sense, and spare analog inputs.
  • ADS1115 support: 0.1 uF VDD decoupling, ADDR tied to GND for default 0x48 unless address conflict appears, ALERT/RDY optional with pullup or no-connect if unused.
  • I2C1 pullups: one pair of 4.7 kOhm pullups from I2C1_SDA and I2C1_SCL to 3V3_LOGIC.
  • Field analog inputs require series resistance, RC filtering, and clamps so ADC input stays within GND - 0.3 V to VDD + 0.3 V.
  • Datasheet check: ADS1115 requires 0.1 uF close to VDD, ADDR selects 0x48/0x49/0x4A/0x4B by tying to GND/VDD/SDA/SCL, ALERT/RDY is open-drain and needs pullup only if used, and analog inputs must remain within GND to VDD in normal operation.
Predator Sniffer
  • Use separate GPIO pins from kernel I2C1.
  • Proposed nets: PRED_I2C_SDA_SNIFF and PRED_I2C_SCL_SNIFF.
  • Add series resistors, ESD protection, configurable pullups, and optional high-impedance buffer if passive sniffing must not disturb the engine bus.
Debug, Status, and Expansion
  • UART debug header: 3V3_LOGIC, GND, UART_DBG_TX, UART_DBG_RX.
  • Status LEDs: 5V_SYS, 3V3_LOGIC, CM5 activity, CAN activity, relay active indicators.
  • Test points: VIN_RAW, VIN_PROT, 5V_SYS, 3V3_LOGIC, GND, ISO_GND_CAN, CAN_H, CAN_L, SPI0 lines, I2C1 lines, relay outputs.
  • Expansion header: spare GPIO, UART, I2C1, 3V3_LOGIC, 5V_SYS, GND, and optional ADC input references.
Proposed High-Level Net Names

Table

DomainNet Names
Power inputVIN_RAW, VIN_PROT, VIN_FUSED, CHASSIS_SHIELD, GND
Rails5V_SYS, 3V3_LOGIC, 5V_CAN_ISO, ISO_GND_CAN, FIELD_VBAT
CM5 power/controlCM5_RUN, CM5_BOOT_MODE, CM5_PWR_EN, CM5_GLOBAL_EN
SPI CANSPI0_SCLK, SPI0_MOSI, SPI0_MISO, SPI0_CS_CAN, CAN_INT, CAN_RST
CAN field sideCAN_TXD, CAN_RXD, CAN_H, CAN_L, CAN_TERM_EN, CAN_SHIELD
I2C1I2C1_SDA, I2C1_SCL, ADS_ALERT_RDY
PredatorPRED_I2C_SDA_SNIFF, PRED_I2C_SCL_SNIFF, PRED_SNIFF_EN
Relay commandsRELAY_START_CMD, RELAY_KILL_CMD, RELAY_FUEL_CMD, RELAY_SPARE_CMD
Relay outputsRELAY_START_OUT, RELAY_KILL_OUT, RELAY_FUEL_OUT, RELAY_SPARE_OUT
DebugUART_DBG_TX, UART_DBG_RX, STATUS_ACT, STATUS_CAN, STATUS_RELAY
CM5 Resource Allocation to Verify

Table

FunctionProposed CM5 ResourceStatus
Kernel I2C1GPIO2 SDA, GPIO3 SCLLocked by requirement
CAN SPISPI0 SCLK/MOSI/MISO plus dedicated CSVerify pin numbers in CM5 datasheet
CAN interruptOne interrupt-capable GPIOSelect exact GPIO during detailed wiring
CAN reset/standbyOptional GPIOsSelect exact GPIO during detailed wiring
Relay commandsFour GPIO outputsSelect exact GPIOs avoiding boot-critical pins
Predator snifferTwo GPIOs not GPIO2/GPIO3Select exact GPIOs avoiding conflicts
UART debugUART0 or alternate UARTVerify with Linux console plan
ADC alertOptional GPIO inputOptional; can omit initially
Schematic Capture Order
  1. Add the power input connector, LT4363 surge/reverse-protection front end, 5 V buck controller, 3.3 V buck, bulk capacitors, and power test points.
  2. Add the two CM5 mezzanine connectors, 5V_SYS bulk/decoupling, RUN/reset, boot-mode pads, UART debug header, and base test points.
  3. Add MCP2518FD, its crystal/oscillator support, ADM3053 isolated CAN, CAN TVS, termination jumper, and CAN connector.
  4. Add four TPS1HTC30-Q1 high-side channels plus opto/digital isolation, current-limit/diagnostic networks, flyback/transient provisions, and relay/load connector.
  5. Add I2C1 pullups/protection, ADS1115 plus analog input RC/protection, Predator sniffer connector/protection, status LEDs, and expansion header.
  6. Run ERC, fix real issues, mark intentionally unused pins no-connect, and only then move to placement/layout.
Implementation Pause Point
The current schematic pass will add the major functional blocks, selected ICs, connectors, mounting holes, and named nets. Detailed pin-by-pin connections and final passive values should proceed only after reviewing this organization and verifying exact CM5 pin allocation.

  • Status

  • Locked Requirements

  • Functional Schematic Groups

  • Selected Parts and Rationale

  • Power Input and Protection

  • Preliminary Power Budget for 5V_SYS

  • 5 V Main Buck

  • 3.3 V Logic Rail

  • CM5 Support

  • CAN Bus

  • Relay / Engine Control

  • I2C and Sensors

  • Predator Sniffer

  • Debug, Status, and Expansion

  • Proposed High-Level Net Names

  • CM5 Resource Allocation to Verify

  • Schematic Capture Order

  • Implementation Pause Point