# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** lonelywafle - **Created:** 11/4/2024 - **Last Updated:** 11/4/2024 - **Visibility:** Public ## Key Components ### U1 — ADS1220IPWR - Manufacturer Part Number: ADS1220IPWR - Part Type: SOP65P640X120-16N - Manufacturer Name: Texas Instruments Inc. - Package or Case Code: SOP65P640X120-16N **Pins:** - ~CS [pin 2] - ~DRDY [pin 14] - AIN0/REFP1 [pin 11] - AIN1 [pin 10] - AIN2 [pin 7] - AIN3/REFN1 [pin 6] - AVDD [pin 12] - AVSS [pin 5] - CLK [pin 3] - DGND [pin 4] - DIN [pin 16] - DOUT/~DRDY [pin 15] - DVDD [pin 13] - REFN0 [pin 8] - REFP0 [pin 9] - SCLK [pin 1] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/lonelywafle/2-layer-jlcpcb-constraints~kx](https://www.flux.ai/lonelywafle/2-layer-jlcpcb-constraints~kx).* --- *Generated from [https://www.flux.ai/lonelywafle/2-layer-jlcpcb-constraints~kx](https://www.flux.ai/lonelywafle/2-layer-jlcpcb-constraints~kx)*