# TMS320F2812ZHHAR (Component)
## Description
TI MCU
TMS320F2812ZHHAR
LFBGA-179_L12.0-W12.0-P0.80-BL_TI_TMS320F2812ZHHAR
LCSC Part Number: C702131
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Manufactured by TI(德州仪器)
## Component Details
- **Owner:** lcsc
- **Created:** 3/17/2026
- **Last Updated:** 3/17/2026
- **Visibility:** Public
- **Part Type:** TI MCU
- **Manufacturer Part Number:** TMS320F2812ZHHAR
- **Package or Case Code:** LFBGA-179_L12.0-W12.0-P0.80-BL_TI_TMS320F2812ZHHAR
- **Manufacturer Name:** TI(德州仪器)
- **LCSC Part Number:** C702131
- **Part Type:** Integrated Circuits
- **Sub-Type:** Embedded Processor
- **Manufacturer:** Texas Instruments
- **MPN:** TMS320F2812ZHHAR
- **Package / Case Code:** LFBGA
- **Pin Count:** 165
- **Logic Function:** Control Unit
## Pins
| Pin | Name | Type |
|-----|------|------|
| A2 | VSSAIO | |
| A3 | ADCINA0 | |
| A4 | ADCINA4 | |
| A5 | VDDA2 | |
| A6 | VDD1 | |
| A7 | SCIRXDA | |
| A8 | XA[16] | |
| A9 | XD[15] | |
| A10 | XA[14] | |
| A11 | XF_XPLLDIS# | |
| A12 | TCK | |
| A13 | TESTSEL | |
| A14 | XA[11] | |
| ADCBGREFIN | E6 | |
| ADCINA1 | D4 | |
| ADCINA5 | E5 | |
| ADCINA6 | D5 | |
| ADCINB7 | F5 | |
| ADCREFM | E4 | |
| ADCREFP | E2 | |
| ADCRESEXT | F2 | |
| AVDDREFBG | E1 | |
| AVSSREFBG | E3 | |
| B1 | ADCINB2 | |
| B2 | VDDAIO | |
| B3 | ADCLO | |
| B4 | ADCINA3 | |
| B5 | ADCINA7 | |
| B6 | XREADY | |
| B7 | XA[17] | |
| B8 | VSS | |
| B9 | XA[15] | |
| B10 | VDD | |
| B11 | XD[14] | |
| B12 | TRST# | |
| B13 | XZCS6AND7# | |
| B14 | VSS | |
| C1 | ADCINB3 | |
| C1TRIP# | E13 | |
| C2 | ADCINB0 | |
| C2TRIP# | E11 | |
| C3 | ADCINB1 | |
| C3TRIP# | F10 | |
| C4 | ADCINA2 | |
| C4TRIP# | N6 | |
| C5 | VSSA2 | |
| C6 | VSS1 | |
| C6TRIP# | K7 | |
| C7 | SCITXDA | |
| C8 | VDD | |
| C9 | EMU1 | |
| C10 | VSS | |
| C11 | XA[12] | |
| C12 | XA[10] | |
| C13 | TDI | |
| C14 | VDD | |
| CANRXA | N13 | |
| CANTXA | N12 | |
| CAP6_QEPI2 | P6 | |
| D1 | ADCINB6 | |
| D2 | ADCINB5 | |
| D3 | ADCINB4 | |
| EMU0 | D11 | |
| H1 | VDD | |
| H2 | MCLKRA | |
| H3 | XD[1] | |
| H4 | MFSXA | |
| H5 | XD[2] | |
| H10 | CAP1_QEP1 | |
| H11 | CAP2_QEP2 | |
| H12 | CAP3_QEPI1 | |
| H13 | XA[5] | |
| H14 | T1CTRIP#_PDPINTA# | |
| J1 | MCLKXA | |
| J2 | MFSRA | |
| J3 | XD[3] | |
| J4 | VDDIO | |
| J5 | XD[5] | |
| J10 | XD[13] | |
| J11 | T1PWM_T1CMP | |
| J12 | XA[4] | |
| J13 | T2PWM_T2CMP | |
| J14 | VSS | |
| L1 | VDD | |
| L2 | VSS | |
| L3 | XD[6] | |
| L4 | PWM11 | |
| L5 | XD[7] | |
| L6 | C5TRIP# | |
| L7 | VDDIO | |
| L8 | TDIRB | |
| L9 | XD[10] | |
| L10 | VDDIO | |
| L11 | VSS | |
| L12 | PWM3 | |
| L13 | PWM4 | |
| L14 | XD[12] | |
| M1 | SPISIMOA | |
| M2 | XA[1] | |
| M3 | XRD# | |
| M4 | PWM12 | |
| M5 | CAP4_QEP3 | |
| M6 | CAP5_QEP4 | |
| M7 | TEST1 | |
| M8 | XD[9] | |
| M9 | X2 | |
| M10 | VSS | |
| M11 | XA[3] | |
| MDRA | G2 | |
| MDXA | G1 | |
| PWM1 | M12 | |
| PWM2 | M14 | |
| PWM5 | K11 | |
| PWM6 | K14 | |
| PWM7 | N2 | |
| PWM8 | P2 | |
| PWM9 | N3 | |
| PWM10 | P3 | |
| SCIRXDB | M13 | |
| SCITXDB | P14 | |
| SPICLKA | K2 | |
| SPISOMIA | N1 | |
| SPISTEA | K4 | |
| T2CTRIP#/EVASOC# | G10 | |
| T3CTRIP#_PDPINTB# | P10 | |
| T3PWM_T3CMP | K5 | |
| T4CTRIP#/EVBSOC# | P11 | |
| T4PWM_T4CMP | N5 | |
| TCLKINA | F13 | |
| TCLKINB | K8 | |
| TDIRA | F14 | |
| TDO | D12 | |
| TEST2 | N7 | |
| TMS | D13 | |
| VDD | G12 | |
| VDD3VFL | N8 | |
| VDDA1 | F4 | |
| VDDIO | E9 | |
| VSS | D10 | |
| VSSA1 | F3 | |
| X1/XCLKIN | K9 | |
| XA[0] | G5 | |
| XA[2] | N10 | |
| XA[6] | G14 | |
| XA[7] | F12 | |
| XA[8] | E12 | |
| XA[9] | D14 | |
| XA[13] | E10 | |
| XA[18] | D7 | |
| XCLKOUT | F11 | |
| XD[0] | G3 | |
| XD[4] | K3 | |
| XD[8] | P7 | |
| XD[11] | N9 | |
| XHOLD# | E7 | |
| XHOLDA# | K10 | |
| XINT1_XBIO# | D9 | |
| XINT2_ADCSOC | D8 | |
| XMP/MC# | F1 | |
| XNMI_XINT13 | E8 | |
| XR/W# | N4 | |
| XRS# | D6 | |
| XWE# | N11 | |
| XZCS0AND1# | P1 | |
| XZCS2# | P13 | |
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*Generated from [https://www.flux.ai/lcsc/tms320f2812zhhar](https://www.flux.ai/lcsc/tms320f2812zhhar)*