# TMS320C6722BRFP200 (Component) ## Description Digital Signal Processors / Controllers (DSPs/DSCs) TMS320C6722BRFP200 EQFP-144_L20.0-W20.0-P0.50-LS22.0-TL-EP5.4 LCSC Part Number: C2871016 JLCPCB Part Class: undefined Manufactured by TI(德州仪器) ## Component Details - **Owner:** lcsc - **Created:** 11/5/2024 - **Last Updated:** 11/5/2024 - **Visibility:** Public - **Part Type:** Digital Signal Processors / Controllers (DSPs/DSCs) - **Manufacturer Name:** TI(德州仪器) - **Package or Case Code:** EQFP-144_L20.0-W20.0-P0.50-LS22.0-TL-EP5.4 - **Manufacturer Part Number:** TMS320C6722BRFP200 - **LCSC Part Number:** C2871016 - **Part Type:** Integrated Circuits - **Sub-Type:** Other - **Manufacturer:** Texas Instruments - **MPN:** TMS320C6722BRFP200 - **Mount Type:** PCB - **Package / Case Code:** 144-EQFP - **Pin Count:** 145 ## Pins | Pin | Name | Type | |-----|------|------| | 1 | VSS | | | 2 | AHCLKX0/AHCLKX2 | | | 3 | AMUTE0 | | | 4 | AMUTE1 | | | 5 | AHCLKX1 | | | 6 | VSS | | | 7 | ACLKX1 | | | 8 | CVDD | | | 9 | ACLKR1 | | | 10 | DVDD | | | 11 | AFSX1 | | | 12 | AFSR1 | | | 13 | VSS | | | 14 | ~{RESET} | | | 15 | VSS | | | 16 | CVDD | | | 17 | CLKIN | | | 18 | VSS | | | 19 | TMS | | | 20 | CVDD | | | 21 | ~{TRST} | | | 22 | OSCVSS | | | 23 | OSCIN | | | 24 | OSCOUT | | | 25 | OSCVDD | | | 26 | VSS | | | 27 | PLLHV | | | 28 | TDI | | | 29 | TDO | | | 30 | VSS | | | 31 | DVDD | | | 32 | ~{EMU[0]} | | | 33 | CVDD | | | 34 | ~{EMU[1]} | | | 35 | TCK | | | 36 | VSS | | | 37 | ~{EM_CAS} | | | 38 | ~{EM_WE} | | | 39 | EM_WE#_DQM[0] | | | 40 | VSS | | | 41 | EM_D[7] | | | 42 | DVDD | | | 43 | EM_D[6] | | | 44 | CVDD | | | 45 | EM_D[5] | | | 46 | EM_D[4] | | | 47 | VSS | | | 48 | EM_D[3] | | | 49 | EM_D[2] | | | 50 | DVDD | | | 51 | EM_D[1] | | | 52 | EM_D[0] | | | 53 | CVDD | | | 54 | VSS | | | 55 | EM_D[15] | | | 56 | EM_D[14] | | | 57 | CVDD | | | 58 | EM_D[13] | | | 59 | EM_D[12] | | | 60 | DVDD | | | 61 | EM_D[11] | | | 62 | VSS | | | 63 | EM_D[10] | | | 64 | EM_D[9] | | | 65 | CVDD | | | 66 | EM_D[8] | | | 67 | EM_WE#_DQM[1] | | | 68 | DVDD | | | 69 | VSS | | | 70 | EM_CLK | | | 71 | EM_CKE | | | 72 | VSS | | | 73 | DVDD | | | 74 | EM_A[11] | | | 75 | EM_A[9] | | | 76 | EM_A[8] | | | 77 | CVDD | | | 78 | VSS | | | 79 | EM_A[7] | | | 80 | EM_A[6] | | | 81 | DVDD | | | 82 | VSS | | | 83 | EM_A[5] | | | 84 | EM_A[4] | | | 85 | CVDD | | | 86 | EM_A[3] | | | 87 | VSS | | | 88 | EM_A[2] | | | 89 | EM_A[1] | | | 90 | CVDD | | | 91 | EM_A[0] | | | 92 | DVDD | | | 93 | EM_A[10] | | | 94 | EM_BA[1] | | | 95 | VSS | | | 96 | EM_BA[0] | | | 97 | ~{EM_CS[0]} | | | 98 | ~{EM_RAS} | | | 99 | VSS | | | 100 | ~{EM_CS[2]} | | | 101 | CVDD | | | 102 | ~{EM_RW} | | | 103 | DVDD | | | 104 | ~{EM_OE} | | | 105 | ~{SPI0_ENA}/I2C1_SDA | | | 106 | VSS | | | 107 | ~{SPI0_SCS}/I2C1_SCL | | | 108 | SPI0_CLK/I2C0_SCL | | | 109 | VSS | | | 110 | SPI0_SIMO | | | 111 | SPI0_SOMI/I2C0_SDA | | | 112 | DVDD | | | 113 | AXR0[0] | | | 114 | VSS | | | 115 | AXR0[1] | | | 116 | AXR0[2] | | | 117 | AXR0[3] | | | 118 | VSS | | | 119 | AXR0[4] | | | 120 | AXR0[5]/~{SPI1_SCS} | | | 121 | AXR0[6]/~{SPI1_ENA} | | | 122 | AXR0[7]/SPI1_CLK | | | 123 | CVDD | | | 124 | VSS | | | 125 | DVDD | | | 126 | AXR0[8]/AXR1[5]/SPI1_SOMI | | | 127 | AXR0[9]/AXR1[4]/SPI1_SIMO | | | 128 | CVDD | | | 129 | VSS | | | 130 | AXR0[10]/AXR1[3] | | | 131 | AXR0[11]/AXR1[2] | | | 132 | CVDD | | | 133 | VSS | | | 134 | AXR0[12]/AXR1[1] | | | 135 | AXR0[13]/AXR1[0] | | | 136 | DVDD | | | 137 | AXR0[14]/AXR2[1] | | | 138 | AXR0[15]/AXR2[0] | | | 139 | ACLKR0 | | | 140 | VSS | | | 141 | AFSR0 | | | 142 | ACLKX0 | | | 143 | AHCLKR0/AHCLKR1 | | | 144 | AFSX0 | | | 145 | EP | | --- *Generated from [https://www.flux.ai/lcsc/tms320c6722brfp200~gz37](https://www.flux.ai/lcsc/tms320c6722brfp200~gz37)*