Part Verification and Datasheet Update

flux

  • Renamed L10 to VDD_DRAM_L10
  • Renamed F10 to I2C3_SDA
  • Renamed P12 to VDD_GPU_P12
  • Renamed P23 to NAND_DATA00
  • Renamed F18 to UART4_TXD

flux

Work done
Success criteria review
  • ✅ Added the missing signal terminals requested in this pass and normalized a substantial set of incorrect signal-to-ball mappings against the NXP datasheet.
  • ✅ Removed several visible duplicate or stale placeholder terminals created during normalization.
  • ✅ Project documentation now records the datasheet-driven reconciliation work.
  • ✅ The project index reports the part-project terminal count as 486, matching the package ball count.
  • ⚠️ A few visible terminals are still not fully normalized in the indexed subset, including ball-style designators such as AG9, E13, W2, and AF2, plus some visible terminals whose Pin Number still equals the signal name.
  • ⚠️ Because the live structured view only exposes part of the project at once, I completed the requested missing-ball fix pass and verified progress, but a final exhaustive all-486 normalization sweep still remains.
Next steps
I can continue with the remaining cleanup pass: rename the last visible ball-style terminals, convert the remaining visible signal-name Pin Number fields to ball coordinates, and then produce a final reconciliation report.
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Pins

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Layout

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Design Notes
Datasheet authority and acceptance criteria
Acceptance criteria for this synchronization pass:
  • Project metadata matches the datasheet for Manufacturer Part Number, Manufacturer Name, Part Type, Datasheet URL, Designator Prefix, and Package or Case Code.
  • Terminal count equals the datasheet package ball count: 486.
  • Footprint pad count equals the package ball count: 486.
  • Ball map uses the datasheet as the single source of truth.
  • Terminal naming is normalized toward signal-name designators, with ball location retained in Pin Number where applicable.
  • Terminal properties are populated consistently: Pin Type, Section, Pin Group, Sub-symbol Designator Suffix, and Pin Orientation.
  • Known typo corrections required by the datasheet-aligned naming scheme include NVCC_ECSPI, ENET_RD3, and TSENSOR_RES_EXT.
  • Remaining review warnings are either resolved or explicitly documented with scope and reason.
MIMX8MM6CVTKZAA terminal normalization
Normalization convention for terminal components in this part project:
  • Pin Type is electrical semantics only.
  • Sub-symbol Designator Suffix is one of PWR, DDR, BOOT, USB, PCIE, MIPI, STOR, IO.
  • Section is a functional subdivision within the sub-symbol.
  • Pin Group is a local adjacency group used to cluster related terminals.
Observed verification target scheme from indexed project data:
  • PWR family:
    • Pin Type: Power In or Ground
    • Section: ARM, SOC, GPU, VPU, DRAM Power, SD Power, USB PHY Power, PCIe Power, MIPI Power, Clock Power, Analog Power, Audio Power, Ground
    • Pin Group: Core Rails, Power Rails, Ground
  • DDR family:
    • Pin Type: DDR
    • Section: DDR Data, DDR Control
    • Pin Group: Address / Command, Byte Lane 0, Byte Lane 2, Byte Lane 3, DQS1
  • BOOT family:
    • Pin Type: Input, Output, ANALOG
    • Section: Boot Straps, JTAG, Power Control, Analog / Test
    • Pin Group: Boot Straps, JTAG, PMIC Control, Test / Sense
  • USB family:
    • Pin Type: PHY
    • Section: USB1, USB2
    • Pin Group: USB1 Data Pair, USB2 Data Pair, VBUS / Detect
  • PCIE family:
    • Pin Type: PHY
    • Section: PCIe
    • Pin Group: Receive Pair, Reference Clock
  • MIPI family:
    • Pin Type: PHY
    • Section: CSI, DSI
    • Pin Group: Clock Pair, Lane 1, Lane 3
  • STOR family:
    • Pin Type: GPIO
    • Section: USDHC1, USDHC2, NAND
    • Pin Group: Clock / Control, Data, Data Bus, Chip Select / Control
  • IO family:
    • Pin Type: GPIO
    • Section: UART1, UART4, GPIO1, I2C, ECSPI1, SAI1, SAI2, SAI3, Ethernet
    • Pin Group: UART1, UART4, GPIO1, I2C Bus, SPI Signals, TX Data, RX Clock, Master Clock, TX Clock, SAI3, RGMII TX, RGMII RX
Current verification limitation:
  • The project total is confirmed as 486 terminal components, but the current project index view does not expose all 486 terminals simultaneously.
  • Verification can confirm indexed terminals and enumerate visible exceptions, but cannot yet prove full 486-terminal coverage from the available index alone.
Initial mappings being enforced:
  • VSS -> Pin Type=Ground, Section=Ground, Pin Group=Ground, Sub-symbol Designator Suffix=PWR
  • VDD_ARM -> Pin Type=Power In, Section=ARM, Pin Group=Core Rails, Sub-symbol Designator Suffix=PWR
  • NVCC_DRAM -> Pin Type=Power In, Section=DRAM Power, Pin Group=Power Rails, Sub-symbol Designator Suffix=PWR
  • VDD_SOC -> Pin Type=Power In, Section=SOC, Pin Group=Core Rails, Sub-symbol Designator Suffix=PWR
  • UART4_TXD -> Pin Type=GPIO, Section=UART4, Pin Group=UART4, Sub-symbol Designator Suffix=IO
Applied cleanup batch
  • Corrected designator typos to match the datasheet:
    • NVCC_ESCPI -> NVCC_ECSPI
    • ENENT_RD3 -> ENET_RD3
    • TESENSOR_RES_EXT -> TSENSOR_RES_EXT
  • Normalized visible repeated VSS terminals to Ground / Ground / Ground / PWR.
  • Normalized visible repeated VDD_ARM terminals to Power In / ARM / Core Rails / PWR.
  • Normalized visible repeated VDD_SOC terminals to Power In / SOC / Core Rails / PWR.
  • Normalized visible repeated NVCC_DRAM terminals to Power In / DRAM Power / Power Rails / PWR.
  • Normalized visible one-off terminals:
    • DRAM_DQ26 -> DDR / DDR Data / Byte Lane 3 / DDR
    • N6 (DRAM_AC15) -> DDR / DDR Control / Address / Command / DDR
    • AG26 (ENET_TD0) -> GPIO / Ethernet / RGMII TX / IO
  • 2026-03-25 reconciliation progress:
    • Added missing signal-named terminals USB1_VBUS, USB2_TXRTUNE, DRAM_AC34, DRAM_DQ02, DRAM_DQ03.
    • Renamed visible ball-style terminals to signal names where verified: F9->I2C1_SDA, N20->VDD_ANA1_1P8, N1->DRAM_AC26, AG18->SAI1_RXD4, V5->DRAM_AC36, W12->NVCC_GPIO1, W26->SD1_DATA7, W27->SD1_DATA6, W4->DRAM_AC22, V4->DRAM_AC23, W5->DRAM_AC37, Y1->DRAM_DQS2_N, D1->DRAM_DQ03, D2->DRAM_DQ02.
    • Corrected Pin Number values to datasheet ball coordinates for SD1_CLK=V14, USB2_VBUS=F23, I2C2_SDA=D4, NVCC_SD1=V20, NAND_CE1_B=P16, DRAM_AC01=F5, USB1_TXRTUNE=E19, DRAM_AC13=N5, DRAM_AC29=V6, NAND_ALE=N21.
    • Removed stale duplicate placeholders F22, E22, P1, and P3 after normalization.

  • Datasheet authority and acceptance criteria

  • MIMX8MM6CVTKZAA terminal normalization

  • Applied cleanup batch