# 82P2282PFG (Component) ## Description Interface - Telecommunications 82P2282PFG TQFP-100_L20.0-W14.0-P0.65-LS24.8-LS18.8-BL LCSC Part Number: C1522114 JLCPCB Part Class: Extended Part Manufactured by RENESAS(瑞萨)/IDT ## Component Details - **Owner:** lcsc - **Created:** 11/8/2024 - **Last Updated:** 11/8/2024 - **Visibility:** Public - **Manufacturer Part Number:** 82P2282PFG - **LCSC Part Number:** C1522114 - **JLCPCB Part Class:** Extended Part - **Manufacturer Name:** RENESAS(瑞萨)/IDT - **Part Type:** Interface - Telecommunications - **Package or Case Code:** TQFP-100_L20.0-W14.0-P0.65-LS24.8-LS18.8-BL ## Distributor Pricing (qty 1) *Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.* | Distributor | Unit Price (qty 1) | Stock | |------------|--------------------|-------| | [Digi-Key](https://www.digikey.com/en/products/detail/renesas-electronics-corporation/82P2282PFG/2018378) | $54.23 | 260 | | [LCSC](https://www.lcsc.com/product-detail/C1522114.html) | $43.0906 | 0 | | [Mouser](https://www.mouser.com/ProductDetail/Renesas-Electronics/82P2282PFG?qs=SmUuHNCnblo83%252BDIrt1aeA%3D%3D) | $57.23 | 0 | - **Part Type:** Integrated Circuits - **Sub-Type:** Logic - **Manufacturer:** Renesas - **MPN:** 82P2282PFG - **Mount Type:** PCB - **Package / Case Code:** 100-TQFP - **Pin Count:** 100 - **Logic Function:** AND ## Pins | Pin | Name | Type | |-----|------|------| | 1 | GPIO | | | 2 | THZ | | | 3 | VDDDC[3] | | | 4 | GNDDC[3] | | | 5 | GNDAP | | | 6 | VDDAP | | | 7 | GNDAB | | | 8 | VDDAB | | | 9 | REFR | | | 10 | GNDAR[2] | | | 11 | RRING[2] | | | 12 | RTIP[2] | | | 13 | VDDAR[2] | | | 14 | VDDAT[2] | | | 15 | GNDAT[2] | | | 16 | GNDAX[2] | | | 17 | TRING[2] | | | 18 | TTIP[2] | | | 19 | VDDAX[2] | | | 20 | VDDAX[1] | | | 21 | TTIP[1] | | | 22 | TRING[1] | | | 23 | GNDAX[1] | | | 24 | GNDAT[1] | | | 25 | VDDAT[1] | | | 26 | VDDAR[1] | | | 27 | RTIP[1] | | | 28 | RRING[1] | | | 29 | GNDAR[1] | | | 30 | NC | | | 31 | IC | | | 32 | MPM | | | 33 | SPIEN | | | 34 | D[0]/SDO | | | 35 | D[1] | | | 36 | D[2] | | | 37 | D[3] | | | 38 | D[4] | | | 39 | D[5] | | | 40 | VDDDIO[1] | | | 41 | D[6] | | | 42 | VDDDC[1] | | | 43 | D[7] | | | 44 | GNDDIO[1] | | | 45 | GNDDC[1] | | | 46 | ~{DS}/~{RD}/SCLK | | | 47 | ~{RW}/~{WR}/SDI | | | 48 | ~{CS} | | | 49 | ~{INT} | | | 50 | IC | | | 51 | IC | | | 52 | A[0] | | | 53 | A[1] | | | 54 | A[2] | | | 55 | A[3] | | | 56 | A[4] | | | 57 | A[5] | | | 58 | GNDDC[2] | | | 59 | GNDDIO[2] | | | 60 | A[6] | | | 61 | VDDDC[2] | | | 62 | A[7] | | | 63 | A[8] | | | 64 | VDDDIO[2] | | | 65 | TSFS[2] | | | 66 | TSIG[2] | | | 67 | TSD[2] | | | 68 | TSCK[2] | | | 69 | RSFS[2] | | | 70 | RSIG[2] | | | 71 | RSD[2] | | | 72 | RSCK[2] | | | 73 | TSFS[1]/MTSFS | | | 74 | TSIG[1]/MTSIG | | | 75 | TSD[1]/MTSD | | | 76 | TSCK[1]/MTSCK | | | 77 | RSFS[1]/MRSFS | | | 78 | RSIG[1]/MRSIG | | | 79 | RSD[1]/MRSD | | | 80 | RSCK[1]/MRSCK | | | 81 | CLK_GEN | | | 82 | IC | | | 83 | IC | | | 84 | ~{RESET} | | | 85 | CLK_SEL[0] | | | 86 | CLK_SEL[1] | | | 87 | CLK_SEL[2] | | | 88 | GNDDC[0] | | | 89 | GNDDIO[0] | | | 90 | REFA_OUT | | | 91 | VDDDC[0] | | | 92 | REFB_OUT | | | 93 | VDDDIO[0] | | | 94 | OSCO | | | 95 | OSCI | | | 96 | TDO | | | 97 | ~{TRST} | | | 98 | TCK | | | 99 | TDI | | | 100 | TMS | | --- *Generated from [https://www.flux.ai/lcsc/82p2282pfg~h8k2](https://www.flux.ai/lcsc/82p2282pfg~h8k2)*