PCB Design Update for DFIG Sensor Interface

L

lavinogada

This is my final AI-credit prompt for this PCB project. Please do the maximum safe completion work in one pass.
Current project:
WRIM DFIG dSPACE Sensor Interface PCB
Current status:
  • Schematic scaling: PASS
  • ERC/passive checks: PASS
  • Placement cleanup: PASS / acceptable routing space
  • Board: 160 mm × 100 mm, 4-layer
  • Current channels: 2 × LEM LA25-NP
  • Voltage channels: 2 × LEM LV25-P
  • Op-amp: OPA4197
  • dSPACE connector: TE Connectivity 5787170-9 custom footprint currently applied as TE_5787170-9_CUSTOM.kicad_mod
  • Routing status: NOT ROUTING READY because connector pin numbering/orientation and final ADC protection still need verification
Design basis:
  • WRIM stator voltage: 380 V line-to-line nominal
  • Stator design margin: 456 V
  • Rotor voltage design level: 120 V
  • Expected current range: 4–6 A RMS
  • dSPACE analog input range: ±10 V
  • Target PCB analog output: approximately ±8.5 V maximum
  • LV25-P primary resistor chains: 100 kΩ using multiple HV resistors in series
  • LA25-NP: 4 primary turns currently selected for safer 6 Arms operation
IMPORTANT:
Do not fabricate or mark the board as fabrication-ready unless all safety-critical issues are closed.
If connector pin numbering/orientation is still uncertain, do not perform final routing. Instead, prepare the project so I can finish verification manually.
Task 1 — Custom connector footprint audit
Audit the custom TE_5787170-9_CUSTOM.kicad_mod footprint against the TE Connectivity 5787170-9 drawing as far as possible.
Check and report:
  1. 100 signal pins present
  2. 2-row geometry
  3. 1.27 mm pitch / centerline
  4. Right-angle PCB receptacle orientation
  5. Through-hole pad arrangement
  6. Boardlock / mechanical retention holes present
  7. Courtyard and keepout around connector body
  8. Pin 1 marker/silkscreen present
  9. Mating-cable direction marked
  10. Any dimensions that still require manual verification against the TE datasheet
If any of these cannot be verified, keep the connector status as:
CUSTOM FOOTPRINT — MANUAL DATASHEET VERIFICATION REQUIRED BEFORE MANUFACTURE.
Task 2 — Pinout and cable-verification discipline
Do not treat the provisional connector pin table as final.
Create a final “continuity-test required” table with:
  • TE pin number
  • PCB net
  • intended dSPACE signal
  • status: PROVISIONAL / VERIFY BY MULTIMETER / SPARE
  • test instruction
Use the current provisional mapping:
  • Pin 1: IA_OUT_ADC
  • Pin 5: AGND for IA return
  • Pin 2: I2_OUT_ADC
  • Pin 6: AGND for I2 return
  • Pin 3: VAB_OUT_ADC
  • Pin 7: AGND for VAB return
  • Pin 4: V2_OUT_ADC
  • Pin 8: AGND for V2 return
  • Pins 99–100: CHASSIS/SHIELD
  • Pins 9–98: NC/SPARE
Add a strong schematic note:
“Final J1 pin mapping must be verified by continuity test between the TE 5787170-9 cable/adapter and the actual dSPACE analog input terminals before final routing or fabrication.”
Task 3 — ADC clamp/protection selection
Select and add a final analog-output protection option if suitable.
Preferred option to evaluate:
  • Bidirectional TVS diode such as SMBJ12CA or a lower-capacitance analog-signal protection alternative if better.
  • The analog outputs are ±10 V maximum dSPACE ADC signals.
  • Protection must not significantly distort the analog measurement signal.
  • Protection should be placed close to J1.
  • Keep the existing series output resistance/protection resistance if appropriate, or recommend changes.
Please decide:
  1. Use SMBJ12CA
  2. Use BAT54S or similar rail-clamp arrangement
  3. Use a lower-capacitance ESD/TVS part
  4. Keep protection as a placeholder pending final part choice
Do not choose a part blindly. If SMBJ12CA capacitance/clamping is not ideal for analog accuracy, recommend the safer alternative and mark it clearly.
Task 4 — Final placement improvements only
Clean placement further if needed:
  • Separate HV LV25-P resistor chains from analog conditioning
  • Keep LA25-NP current paths short and away from op-amp inputs
  • Keep protection components near J1
  • Keep test points top-accessible
  • Keep AGND and CHASSIS separate unless intentionally bonded
  • Keep silkscreen readable
  • Add labels for IA, I2, VAB, V2, AGND, +15V, -15V, CHASSIS, J1 Pin 1, and cable direction
Task 5 — Conditional routing
Only route the PCB if all of the following are true:
  • TE 5787170-9 footprint geometry is sufficiently verified
  • Pin 1 and connector orientation are clear
  • Boardlock holes are included
  • ADC protection part is selected and placed
  • No safety-critical uncertainty remains except cable continuity verification
If these are not all true:
  • Do not route final traces.
  • Instead, create a “pre-routing package” with clean placement, annotated blockers, and manual verification steps.
Task 6 — Final output
Return a concise final status report with:
  1. ROUTED or NOT ROUTED
  2. FABRICATION READY or NOT FABRICATION READY
  3. Remaining blockers
  4. Connector footprint verification status
  5. Connector pinout verification status
  6. ADC protection decision
  7. DRC/ERC status
  8. Airwire status
  9. BOM issues
  10. Exact manual checks I must perform before manufacturing
If in doubt, choose safety and mark the board NOT FABRICATION READY.

flux

Final focused update completed.
  1. J1 footprint: kept as the custom TE 5787170-9 footprint and documented as provisional / must be manually verified against the TE drawing before manufacture.
  2. Pin mapping: documented the required continuity-test table for J1 pins 1–8, 99, and 100.
  3. ADC protection: added D1–D4 PESD12VL1BA-N TVS diodes from each protected ±10 V analog output to AGND near J1.
  4. Placement: cleaned placement around J1; D1–D4 are close to the protected dSPACE output pins.
  5. Silkscreen: added labels for J1 pin 1, cable/mating direction, analog output/return labels, and power/ground/chassis labels.
  6. Routing: final traces were not routed, per your instruction and because J1/cable continuity still needs manual verification.
  7. Reviews: remaining layout errors are expected airwires because the board is intentionally unrouted; no final manufacturing export was generated.
  8. BOM: updated BOM now includes 4× PESD12VL1BA-N and J1 listed with MPN 5787170-9.
  9. Fabrication status: NOT ready for fabrication yet until J1 footprint dimensions, pin 1 orientation, cable direction, and dSPACE continuity are physically verified.
  10. Documentation: I created the project file “Pre-Routing Verification Package — WRIM DFIG dSPACE Sensor Interface” with the full footprint audit, continuity table, ADC protection rationale, placement summary, and remaining blockers.
Show manual checks
Review remaining blockers
Check BOM issues
Show continuity table
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Files

Schematic

Layout

3D View

R30
Resistance
20000 ohms
R25 P2 - U3 +HV
J6 Pin_2 - U1 -
R17 P2 - C5 P1
J6 Pin_1 - U1 +
J6 Pin_4 - J1 99
R9
Resistance
10000 ohms
R22
Resistance
20000 ohms
R30 P2 - U4 +HV
R20 P2 - C8 P1
J6 Pin_3 - R1 P2
U1 M - R1 P1
U3 M - R3 P1
J6 Pin_3 - R1 P2
J6 Pin_2 - U1 -
U1 OUT - U1 IN
U5 -IN_D - R12 P1
U5 -IN_B - R10 P1
U5 OUT_C - R15 P1
J6 Pin_3 - R1 P2
R26 P2 - R27 P1
J1 100 - TP8
R28 P2 - R29 P1
U5 -IN_C - R11 P1
R28
Resistance
20000 ohms
J1 100 - TP8
J6 Pin_3 - R1 P2
R3
Resistance
180 ohms
R7 P2 - C3 P1
R19 P2 - C7 P1
R17
Resistance
1000 ohms
U1 M - R1 P1
J6 Pin_3 - R1 P2
J6 Pin_2 - U1 -
U3 M - R3 P1
J1 8 - TP7
R30 P2 - U4 +HV
R6 P2 - C2 P1
R16
Resistance
100000 ohms
U1 OUT - J4 Pin_2
R19
Resistance
1000 ohms
R21
Resistance
20000 ohms
R8 P2 - C4 P1
U2 OUT - U2 IN
U2 OUT - J5 Pin_2
R23 P2 - R24 P1
R18
Resistance
1000 ohms
R20 P2 - C8 P1
J2 Pin_1 - R21 P1
R18 P2 - C6 P1
R6
Resistance
1000 ohms
U3 -HV - J2 Pin_2
R2
Resistance
100 ohms
U2 OUT - U2 IN
U2 OUT - U2 IN
R29
Resistance
20000 ohms
U2 OUT - J5 Pin_2
U5 -IN_C - R11 P1
J6 Pin_1 - U1 +
R25 P2 - U3 +HV
U4 M - R4 P1
J6 Pin_3 - R1 P2
U2 OUT - U2 IN
R24 P2 - R25 P1
R14
Resistance
13300 ohms
U1 OUT - U1 IN
J6 Pin_3 - R1 P2
R11
Resistance
10000 ohms
R7 P2 - C3 P1
R22 P2 - R23 P1
J6 Pin_3 - R1 P2
R20 P2 - C8 P1
R8 P2 - C4 P1
R13
Resistance
13300 ohms
R20
Resistance
1000 ohms
J6 Pin_2 - U1 -
R23 P2 - R24 P1
J6 Pin_1 - U1 +
J6 Pin_3 - R1 P2
J6 Pin_1 - U1 +
J6 Pin_3 - R1 P2
R17 P2 - C5 P1
R28 P2 - R29 P1
R19 P2 - C7 P1
J2 Pin_1 - R21 P1
R17 P2 - C5 P1
J6 Pin_1 - U1 +
U5 -IN_A - R9 P1
U5 -IN_D - R12 P1
J4 Pin_1 - U1 IN
J6 Pin_1 - U1 +
R27 P2 - R28 P1
R5 P2 - C1 P1
U5 -IN_C - R11 P1
J6 Pin_3 - R1 P2
J6 Pin_3 - R1 P2
R27 P2 - R28 P1
R19 P2 - C7 P1
U1 OUT - U1 IN
J6 Pin_3 - R1 P2
U5 OUT_A - R13 P1
J4 Pin_1 - U1 IN
R26
Resistance
20000 ohms
U5 OUT_D - R16 P1
U5 OUT_D - R16 P1
U4 -HV - J3 Pin_2
R7
Resistance
1000 ohms
J6 Pin_2 - U1 -
U5 -IN_A - R9 P1
R20 P2 - C8 P1
R1
Resistance
100 ohms
R6 P2 - C2 P1
U2 M - R2 P1
J6 Pin_3 - R1 P2
U5 OUT_A - R13 P1
J5 Pin_1 - U2 IN
R29 P2 - R30 P1
U3 M - R3 P1
R18 P2 - C6 P1
J6 Pin_3 - R1 P2
U5 OUT_C - R15 P1
U3 -HV - J2 Pin_2
U1 M - R1 P1
J6 Pin_4 - J1 99
U5 OUT_C - R15 P1
R21 P2 - R22 P1
R5 P2 - C1 P1
U4 -HV - J3 Pin_2
J6 Pin_2 - U1 -
U5 OUT_B - R14 P1
R25
Resistance
20000 ohms
R8 P2 - C4 P1
U5 OUT_B - R14 P1
J3 Pin_1 - R26 P1
U5 OUT_B - R14 P1
J6 Pin_2 - U1 -
J6 Pin_3 - R1 P2
R20 P2 - C8 P1
R18 P2 - C6 P1
U5 -IN_B - R10 P1
R5 P2 - C1 P1
J6 Pin_3 - R1 P2
U1 OUT - U1 IN
U2 M - R2 P1
R26 P2 - R27 P1
J1 8 - TP7
U2 M - R2 P1
J6 Pin_3 - R1 P2
U5 -IN_B - R10 P1
J6 Pin_1 - U1 +
R4
Resistance
180 ohms
R18 P2 - C6 P1
J6 Pin_1 - U1 +
R10
Resistance
10000 ohms
J6 Pin_3 - R1 P2
U2 OUT - U2 IN
J6 Pin_3 - R1 P2
R23
Resistance
20000 ohms
U5 OUT_D - R16 P1
U5 -IN_A - R9 P1
U1 OUT - J4 Pin_2
R6 P2 - C2 P1
R24 P2 - R25 P1
R19 P2 - C7 P1
U1 OUT - U1 IN
U4 M - R4 P1
U4 M - R4 P1
R17 P2 - C5 P1
J6 Pin_2 - U1 -
J6 Pin_3 - R1 P2
R29 P2 - R30 P1
R17 P2 - C5 P1
R12
Resistance
10000 ohms
R19 P2 - C7 P1
J6 Pin_3 - R1 P2
R22 P2 - R23 P1
R5
Resistance
1000 ohms
J6 Pin_3 - R1 P2
R24
Resistance
20000 ohms
R8
Resistance
1000 ohms
J5 Pin_1 - U2 IN
U1 OUT - U1 IN
J6 Pin_3 - R1 P2
U5 -IN_D - R12 P1
J6 Pin_1 - U1 +
R27
Resistance
20000 ohms
R7 P2 - C3 P1
J6 Pin_3 - R1 P2
R21 P2 - R22 P1
J6 Pin_3 - R1 P2
R18 P2 - C6 P1
U2 OUT - U2 IN
J3 Pin_1 - R26 P1
U5 OUT_A - R13 P1
J6 Pin_2 - U1 -
R15
Resistance
19100 ohms
TP2
C12
Capacitance
10 uF
J2
C2
Capacitance
10 nF
J6
C1
Capacitance
10 nF
C9
Capacitance
100 nF
C5
Capacitance
4.7 nF
J4
TP1
C7
Capacitance
4.7 nF
C6
Capacitance
4.7 nF
C3
Capacitance
10 nF
TP5
TP7
TP8
C11
Capacitance
10 uF
C10
Capacitance
100 nF
TP4
C4
Capacitance
10 nF
J5
TP3
TP6
J3
C8
Capacitance
4.7 nF
U1
U4
D3
U3
D2
U2
D1
D4
U5
J1
Pre-Routing Verification Package — WRIM DFIG dSPACE Sensor Interface
Status
  • Routing: NOT ROUTED
  • Fabrication readiness: NOT FABRICATION READY
  • Reason: dSPACE cable/adapter pin continuity and TE 5787170-9 custom footprint must still be manually verified before routing/fabrication.
J1 custom footprint audit
Connector: TE Connectivity 5787170-9, AMPLIMITE 0.50, 100-position, 2-row, right-angle through-hole PCB receptacle.
Applied asset: TE_5787170-9_CUSTOM.kicad_mod

Table

Audit itemStatusNotes
100 signal pins presentPASS FROM GENERATED FOOTPRINTGenerated as 100 through-hole signal contacts. Manual KiCad/TE drawing inspection still required.
2-row geometryPASS FROM GENERATED FOOTPRINTGenerated as two contact rows.
1.27 mm pitch / centerlinePASS FROM TE DRAWING + GENERATED FOOTPRINTColumn pitch generated at 1.27 mm.
Row spacingPASS FROM TE DRAWING + GENERATED FOOTPRINTGenerated from TE drawing row spacing.
Right-angle PCB receptacle orientationPROVISIONALLayout marks cable/mating direction, but real cable/adapter orientation must be checked.
Through-hole pad arrangementPASS FROM GENERATED FOOTPRINTContact pads generated as PTH.
Boardlock / mechanical retention holesPASS FROM GENERATED FOOTPRINTTwo mechanical boardlock holes generated from TE drawing dimensions.
Courtyard / keepout around connector bodyPARTIALSilkscreen/body outline and note present; verify courtyard against mechanical envelope before fabrication.
Pin 1 marker/silkscreenPROVISIONALPin 1 label added; verify against TE drawing and physical cable.
Mating-cable direction markedPROVISIONALCable/mating direction label added; verify physically.
Dimensions requiring manual verificationREQUIREDBoardlock spacing, PCB edge relationship, body envelope/courtyard, pin numbering, mating direction, and adapter continuity.
Connector status remains: CUSTOM FOOTPRINT — MANUAL DATASHEET VERIFICATION REQUIRED BEFORE MANUFACTURE.
Final continuity-test required connector table

Table

TE pinPCB netIntended dSPACE signalStatusTest instruction
1IA_OUT_ADCIA_OUT_ADCVERIFY BY MULTIMETERProbe J1 pin 1 to actual dSPACE IA analog input terminal.
5AGNDIA_RETURN_AGNDVERIFY BY MULTIMETERProbe J1 pin 5 to IA return / analog ground terminal.
2I2_OUT_ADCI2_OUT_ADCVERIFY BY MULTIMETERProbe J1 pin 2 to actual dSPACE I2 analog input terminal.
6AGNDI2_RETURN_AGNDVERIFY BY MULTIMETERProbe J1 pin 6 to I2 return / analog ground terminal.
3VAB_OUT_ADCVAB_OUT_ADCVERIFY BY MULTIMETERProbe J1 pin 3 to actual dSPACE VAB analog input terminal.
7AGNDVAB_RETURN_AGNDVERIFY BY MULTIMETERProbe J1 pin 7 to VAB return / analog ground terminal.
4V2_OUT_ADCV2_OUT_ADCVERIFY BY MULTIMETERProbe J1 pin 4 to actual dSPACE V2 analog input terminal.
8AGNDV2_RETURN_AGNDVERIFY BY MULTIMETERProbe J1 pin 8 to V2 return / analog ground terminal.
99CHASSISCHASSIS/SHIELDVERIFY BY MULTIMETERProbe J1 pin 99 to cable shield/chassis contact if used.
100CHASSISCHASSIS/SHIELDVERIFY BY MULTIMETERProbe J1 pin 100 to cable shield/chassis contact if used.
9-98NC / spareSPARESPAREConfirm no unintended continuity to dSPACE analog/HV/current lines.
Strong schematic note: Final J1 pin mapping must be verified by continuity test between the TE 5787170-9 cable/adapter and the actual dSPACE analog input terminals before final routing or fabrication.
ADC protection decision
Selected protection: PESD12VL1BA-N low-capacitance bidirectional ESD/TVS diode, one per analog output, from protected ADC output node to AGND near J1.
Why not SMBJ12CA: SMBJ12CA is robust but has unnecessarily high capacitance for measurement lines and is a surge suppressor rather than a precision ADC limiter.
Why not BAT54S rail clamp: rail clamp requires known safe clamp rails. Clamping to ±15 V is not adequate for a ±10 V ADC, and clamping to unknown dSPACE rails could inject current/back-power the equipment.
PESD12VL1BA-N datasheet values used:
  • VRWM: 12 V
  • VBR min: 13.3 V at 1 mA
  • IR max: 1 uA at 12 V, 25 C
  • Cj max: 30 pF at 0 V, 1 MHz
  • VC max: 26 V at IPP 10 A, 8/20 us
Design note: This is ESD/transient protection, not a precision ±10 V hard limiter. The existing 1 kΩ series output resistance limits fault current. If dSPACE absolute maximum input is only ±10 V with no internal tolerance, use a verified precision limiter or manufacturer-approved clamp scheme before fabrication.
Placement / floorplan summary
  • J1 placed on left board edge with cable/mating direction label.
  • D1-D4 placed close to J1 protected analog output pins.
  • OPA4197 and analog gain/filter network grouped in low-voltage analog zone inboard of J1.
  • LV25-P sensors and 100 kΩ high-voltage resistor chains kept on machine/high-voltage side.
  • LA25-NP sensors and current connectors kept away from sensitive op-amp inputs.
  • Test points are top-side accessible.
  • AGND and CHASSIS remain separate nets.
Remaining blockers before routing/manufacturing
  1. Verify TE_5787170-9_CUSTOM.kicad_mod against TE drawing 5787170 rev B1, especially boardlocks, PCB edge relationship, and body/courtyard.
  2. Verify J1 pin 1 orientation and mating cable exit direction on the actual cable/adapter.
  3. Perform continuity test from J1 pins to actual dSPACE analog input terminals.
  4. Confirm dSPACE analog input absolute maximum rating and whether PESD12VL1BA-N + 1 kΩ is adequate, or whether a precision limiter is required.
  5. Confirm CHASSIS/SHIELD pins and whether shield should remain isolated from AGND or be bonded via a defined network.
  6. After manual verification, route and re-run full DRC/ERC before fabrication.

  • Status

  • J1 custom footprint audit

  • Final continuity-test required connector table

  • ADC protection decision

  • Placement / floorplan summary

  • Remaining blockers before routing/manufacturing