Project Start Planning

kkarthikeya

kkarthikeya

Check ERC for unconnected pins, power conflicts, and other schematic errors.

flux

I can’t run or inspect ERC because the account currently has no available ACUs. No ERC verification was completed in this session.
Remaining checks:
  • Unconnected and dangling pins
  • Power-output conflicts and incorrect power-net types
  • All 18 servo connector signal/power/ground connections
  • PCA9685 address, OE, I²C, VDD, V+ and decoupling
  • HC-SR04 ECHO divider and ESP32 GPIO connections
  • Separation of +5V_SERVO and +5V_ESP32, with common GND
kkarthikeya

kkarthikeya

Re-run ERC for unconnected pins, power conflicts, and any other schematic errors.

flux

I still can’t re-run ERC because the account has no available ACUs. No new schematic checks or changes were made.
Once ACUs are available, the remaining task is to run ERC and inspect unconnected pins, power conflicts, all 18 servo ports, both PCA9685s, the HC-SR04 divider, and separation of +5V_SERVO from +5V_ESP32.
Check ERC later
Inspect power nets
Review unconnected pins
Check servo interfaces
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Files

Schematic

Layout

Preview

Project Specification
Project Overview
  • Status: Schematic review checkpoint
  • ESP32-based controller for a six-legged robot with exactly 18 external MG90S servo ports, two PCA9685 PWM controllers, and an HC-SR04 interface.
Intended Use
  • Student prototype powered from an external 2S LiPo.
  • ESP32 DevKit V1 is soldered directly to the PCB.
  • Servos, battery, ultrasonic module, 20 A servo buck, and main switch are external.
What the Device Should Do
  • Generate 18 independent servo PWM signals.
  • Operate two PCA9685 devices on one 3.3 V I2C bus at addresses 0x40 and 0x41.
  • Power servo and logic loads from independent battery-fed 5 V converters with common GND.
  • Read an HC-SR04 through a protected 3.3 V ECHO input.
Main Features
  • U1 ESP32 DevKit V1.
  • U2/U3 PCA9685PW; U2 uses LED0-15 and U3 uses LED0-1.
  • J5-J22: 18 individual 3-pin servo headers, arranged logically as six legs × three joints.
  • J23: HC-SR04 header.
  • J1: JST VH 2-pin battery input.
  • F1: 20 A MINI blade fuse holder.
  • J2: two-wire external high-current main-switch loop.
  • J3/J4: four-terminal external 5.0 V / 20 A servo-buck interface, split into 32 A input and output terminal blocks.
  • U4: TSR2-2450 independent 5 V / 2 A logic buck.
  • H1-H4: four mechanical mounting holes.
System Architecture
Diagram



  
    
  
  
    
  






























2S LiPo via J1
20 A fuse
External DC-rated switch via J2
External fixed 5 V / 20 A buck via J3/J4
TSR2-2450 5 V / 2 A
+5V_SERVO
+5V_ESP32
ESP32 DevKit V1
3.3 V
PCA9685 U2
PCA9685 U3
Servo ports 1-16
Servo ports 17-18
HC-SR04 connector
Hardware Subsystems
Battery and Protection
  • 2S LiPo: 7.4 V nominal, 8.4 V maximum.
  • Battery positive path: J1 → F1 → external switch loop J2 → two converter branches.
  • Common GND is shared, while the schematic keeps high-current servo and logic power blocks distinct.
Servo Power
  • J3 is VIN+/VIN- to the external converter; J4 is VOUT+/VOUT- from the converter.
  • Required external module: fixed 5.0 V, target 20 A.
  • +5V_SERVO powers all 18 servo-header 5 V pins.
  • C3 = 2200 uF bulk capacitance.
Logic Power
  • U4 TSR2-2450: fixed 5 V, 2 A logic rail.
  • C6 = 22 uF / 50 V at the switched regulator input.
  • C4 = 100 uF and C5 = 0.1 uF at ESP32 VIN.
Compute and PWM
  • U1 GPIO21 = SDA, GPIO22 = SCL, GPIO17 = HC_TRIG, GPIO16 = ESP32_ECHO.
  • U2 address straps all LOW: 0x40.
  • U3 A0 HIGH and A1-A5 LOW: 0x41.
  • OE is tied LOW for enabled outputs; EXTCLK is grounded because it is unused.
  • R3/R4 are the only I2C pull-ups, both 4.7 kΩ to 3.3 V.
  • C1/C2 are 0.1 uF local VDD decoupling capacitors.
PCA9685 Supply Clarification
  • The selected bare PCA9685PW IC has VDD/VSS but no V+ terminal. Therefore +5V_SERVO is routed directly to the servo connectors, while each PCA9685 logic supply remains at 3.3 V. A breakout-board-style V+ pin cannot be connected on this IC.
Ultrasonic Interface
  • J23 is powered from +5V_ESP32.
  • TRIG is direct from GPIO17.
  • ECHO → R1 1 kΩ → ESP32_ECHO; R2 2 kΩ connects ESP32_ECHO to GND.
Interfaces and Connections

Table

InterfaceAssignment
I2C SDAGPIO21
I2C SCLGPIO22
HC-SR04 TRIGGPIO17
HC-SR04 ECHOGPIO16 through 1 kΩ / 2 kΩ divider
PCA9685 U2PWM channels for J5-J20
PCA9685 U3PWM channels for J21-J22; LED2-15 intentional NC
Power and Runtime Expectations
  • Servo design target: 10-15 A aggregate peaks at 5 V.
  • Logic converter capacity: 2 A at 5 V.
  • Runtime depends on LiPo capacity, servo duty cycle, gait, and mechanical loading.
Power Tree and Power Budget

Table

LoadOutput power caseApproximate battery current at 6.5 V
Servo rail peak5 V × 15 A = 75 W~12.8 A at 90% efficiency
Logic rail full rating5 V × 2 A = 10 W~1.6 A at 94% efficiency
Combined conservative case85 W output~14.5 A
  • A 20 A fuse provides margin over the conservative input estimate.
  • The JST VH battery connector is rated 10 A and is below the conservative peak estimate; this is a known current-rating risk and must be reviewed before layout/fabrication.
Manufacturing and Assembly Expectations
  • SMD passives and PCA9685 ICs; through-hole external connectors and regulator module.
  • High-current terminal blocks are rated above the design target.
  • Do not start PCB placement until the schematic checkpoint is approved.
Firmware-Relevant Hardware Requirements
  • Initialize I2C on GPIO21/22.
  • Use PCA9685 addresses 0x40 and 0x41.
  • Configure U2 channels 0-15 and U3 channels 0-1 only.
  • Use GPIO17 as output and GPIO16 as input for HC-SR04.
Physical Design Expectations
  • Six clearly labeled servo groups, each containing coxa, femur, and tibia ports.
  • Keep the ESP32 antenna region clear during layout.
  • Route +5V_SERVO and GND for 10-15 A peaks using high-current layout practices.
  • Four mounting holes.
Important Design Decisions
  • No servo motors are PCB components.
  • The 20 A servo converter and main switch are represented as honest external interfaces rather than underspecified on-board circuits.
  • +5V_SERVO and +5V_ESP32 are independently generated.
  • All grounds are common.
Assumptions
  • External switch is SPST and rated at least 20 A DC at the battery voltage.
  • External servo converter accepts the complete 2S LiPo operating range and supplies regulated 5.0 V at the required transient current.
  • Main-switch and servo-buck wiring uses suitably sized conductors and terminals.
Change Notes
  • Completed logical schematic wiring and intentional no-connect marking.
  • Selected TSR2-2450 logic regulator, JST VH battery connector, MINI blade fuse holder, and 32 A external power interfaces.
  • Recorded the PCA9685 V+ architectural mismatch and JST current-rating risk.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Battery and Protection

  • Servo Power

  • Logic Power

  • Compute and PWM

  • PCA9685 Supply Clarification

  • Ultrasonic Interface

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes