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Thought for 53 sec
F40 Crossbar Emulator โ Project Doc Blurb
Purpose
- Implements a 4ร8 analog crossbar emulator for vector-matrix multiply (VMM): column currents reflect weighted sums of four row inputs per column.
- This is the โexcitatoryโ bank (8 columns); an inhibitory bank can be added later.
Architecture
- 4 rows ร 8 columns of synapses (32 total). Each synapse multiplies a shared row input by an individual weight voltage.
- Eight quad DAC channels (one quad per column) generate the weight voltages.
- Two quad op-amps implement eight inverting column summers (one per column, 4 inputs each).
- A bus transceiver level-shifts MCU row spikes to the 5 V row domain.
Key interfaces
- Rows (inputs): ROW0, ROW1, ROW2, ROW3 (post-level-shift, nominal 5 V).
- Column outputs (to next stage): V_COL_SUM[0..7].
- I2C bus: SDA, SCL (3.3 V logic), pulled up by 4.7 kฮฉ.
- Header: CROSSBAR_I2C 2ร5 (pins: 3V3, GND, SDA, SCL, LS_DIR, LS_OE_N, ROW0_MCU, ROW1_MCU, ROW2_MCU, ROW3_MCU).
- Test points: TP_ROW0..3, TP_COL0..7, TP_WEIGHT_SAMPLE.
Power rails
- Analog: +5 V (V5A), โ5 V (VN5A).
- Digital: +3.3 V (V3D).
- Grounding: AGND_SUM is a local bias net for the column summers and is tied to GND at a single 0 ฮฉ link (net-tie). Do not pour AGND_SUM planes.
Design details
- Column summers: inverting configuration; 4ร input resistors per column and 1ร feedback resistor (nominal 10 kฮฉ each for unity-weighted sum).
- Non-inverting pin biasing: each summer IN+ references ground only through a resistor to AGND_SUM (no direct IN+ to GND ties).
- PerโIC decoupling: 100 nF at each IC supply; place close to pins.
- DAC bulk caps: 10 ยตF per DAC on VDD, plus local 100 nF.
I2C addressing
- Excitatory bank: 0x60โ0x67 (one quad per column).
- Reserve 0x68โ0x6F for an optional inhibitory bank.
PCB constraints
- Board size: 100 mm ร 80 mm.
- Keep analog paths short; place decouplers within 5 mm of pins.
- Do not pour AGND_SUM; maintain a single-point tie to GND.
Verification checklist
- ERC/DRC clean; no shorted components.
- IN+ pins of all summers biased via resistor to AGND_SUM only.
- I2C pull-ups present; SDA/SCL at 3.3 V.
- All row lines driven through the level shifter; DIR and OE set correctly.
- All ICs have 100 nF decouplers; all DACs have 10 ยตF bulk.
- Test points placed and named as listed.
go
Thought for 48 sec
I can update the project description with your F40 Crossbar Emulator documentation blurb. Iโll apply the change now.
Once itโs in, re-run the review to confirm the โProject has no documentationโ item clears. If you want the same text also saved as a project property (e.g., Docs:F40), let me know and I can add that too.
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