Firmware Audit Review

flux

Read-only audit completed; no project mutations were made.
Files reviewed
  • project-specification
  • design-notes
  • Asset inventory: pwm-output-step-response.png, analog-bandpass-bode.png
Confirmed against the live schematic
  • ATtiny1616 mapping for PA4/PA5 ADC inputs, PA6/PA7/PB5 calibration ADCs, PB4 RPM, PB3/PB2 channel selects, PB0 PWM, and PA0 UPDI.
  • J6 wiring: pin 1 UPDI through R37, pin 2 +5 V, pin 6 GND.
  • Output formula is correct: VOUT = 0.5016 V + 3.9968 V × duty.
  • RPM calculations are correct: approximately 4.359 V high, 128 µs time constant, and 1.242 kHz cutoff.
  • 2 pulses/revolution gives 266.7 Hz at 8000 RPM.
Discrepancies / missing verification artifacts
  • No firmware source, project configuration, or firmware project file exists. Consequently, compilability, runtime processing, watchdog behavior, PWM setup, ADC sampling, channel logic, and the claimed configurable 2 pulses/revolution default cannot be verified.
  • No dependency list, exact build command, flash command, programmer selection, UPDI adapter wiring procedure, fuse configuration, or post-flash validation is documented.
  • No board bring-up/test-plan file exists. Current files lack a complete current-limited first-power procedure, mandatory common-ground instructions, programmer target-power precautions, staged sensor/ECU connection safety, and numeric pass/fail tables.
  • The schematic symbol labels PB2 as TOSC1/PB2, while design-notes calls it PB2/TOSC2; this naming conflict should be checked against the ATtiny1616 datasheet/library part.
  • Settling-time, ripple, and band-response claims are summarized in design-notes, but no simulation source/configuration file is present, so the plots cannot be independently reproduced from project files.
  • project-specification still says pulses/revolution is unconfirmed, while design-notes asserts a configurable firmware default; these are not necessarily incompatible, but the implementation evidence is absent.
Create bring-up test plan
Check PB2 pin name
Document firmware requirements
Resolve PPR documentation
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Files

Schematic

Layout

Preview

1.8T Knock Signal Conditioner thumbnail