• Prototype and field controller for a motorized large-format camera focusing mechanism.
• Operates from a 12 V TalentCell-style battery in the field or USB-C for logic-only bench operation and programming.
• Drives one four-wire NEMA17 stepper motor.
• Supports live camera view, display UI, removable storage, range/focus sensors, and rotary controls.
• Four-layer production-intent prototype with hand-accessible connectors and through-hole parts where practical.

• Run the ProView LF r69 firmware after updating the TFT CS/RST definitions for this corrected hardware mapping.
• Capture OV5640 DVP video using ESP32-S3 PSRAM for frame buffers.
• Render a 320 x 240 landscape UI on an ST7789 240 x 320 panel.
• Store data on a microSD card over SPI.
• Command a TMC2240 module using a dedicated software-SPI bus and STEP signal.
• Connect up to eight isolated I2C branches through a TCA9548A at address 0x70.
• Operate from 12 V alone or USB-C 5 V alone, with motor VM disabled when no 12 V source is present.
• Avoid ESP32 brownouts and prevent motor-driver transients from propagating into logic signals or rails.

• ESP32-S3-WROOM-1-N16R8 with 16 MB flash and 8 MB OPI PSRAM.
• Native USB-C USB 2.0 device interface for flashing, serial debug, and 5 V input.
• Socketed BIGTREETECH TMC2240 in standard 2 x 8, 2.54 mm StepStick format.
• JST-VH 3.96 mm four-position motor output connector.
• ST7789 SPI TFT header plus parallel 0.5 mm FPC footprint; no touch controller.
• 24-pin, 0.5 mm DVP camera FPC interface.
• Push-push microSD socket in SPI mode.
• TCA9548A I2C mux and eight Qwiic/STEMMA-QT connectors.
• BOOT and RESET/EN tactile buttons.
• Test points for 12V, VM, 5V, 3V3, GND, STEP, CS, SCK, MOSI, and MISO.
• Four M3 corner mounting holes.

Diagram

• ESP32-S3-WROOM-1-N16R8 module; PSRAM is mandatory.
• GPIO0 is BOOT-only and connects only to the BOOT button SW2.
• GPIO45 is intentionally unused and must remain unconnected because it is a VDD_SPI strapping pin.
• EN has a 10 k pull-up and an RC delay capacitor; RESET button pulls EN low.
• BOOT button pulls GPIO0 low.
• Native USB is used instead of a USB-UART bridge. Optional DTR/RTS auto-program circuitry is not required for the first revision unless a separate control interface is added.
• Keep the module antenna at a board edge with a copper and component keepout on every layer.

• Standard StepStick 2 x 8 socket for a BIGTREETECH TMC2240 module.
• Dedicated software-SPI interface, not shared with display or SD.
• Firmware-fixed signals: STEP GPIO18, CSN GPIO43, SCK GPIO44, SDI/MOSI GPIO47, SDO/MISO GPIO48.
• DIR and EN are tied low by default as required by r69. Provide removable 0 ohm links or solder jumpers so this behavior can be altered in a future firmware revision without cutting traces.
• Each ESP-to-TMC logic signal uses a 100 ohm series resistor at the ESP end and a low-capacitance clamp to 3.3 V and GND.
• Optional ISO7741-class isolation footprint for CS, SCK, MOSI, and MISO; default assembly uses 0 ohm bypass links. STEP remains protected but non-isolated unless isolation is expanded in a later revision.
• TMC VIO is supplied from a ferrite-bead-filtered 3.3 V branch.
• VM local capacitance: 470 uF, 25 V low-ESR electrolytic plus 10 uF and 100 nF ceramics at the socket.

• Display SPI: MOSI GPIO38, SCK GPIO39, DC GPIO42, CS GPIO5, RST GPIO3, BL GPIO1.
• Firmware must be updated to use TFT CS GPIO5 and TFT RST GPIO3.
• Backlight is switched by a logic-level MOSFET and controlled by GPIO1 PWM.
• microSD shares GPIO38 and GPIO39; MISO GPIO40 and CS GPIO41 are dedicated to SD.
• Use appropriate pull-ups on SD SPI control/data pins and local bulk/decoupling capacitance.

• Approved camera is YDS-PAA40-OV5640-1B on exact FH12-24S-0.5SH(55) bottom-contact 24-pin, 0.5 mm FPC connector.
• Module raw rails are supplied externally: AVDD/DOVDD/AFVDD at 2.8 V and DVDD at 1.5 V from dedicated TLV755 fixed LDOs.
• ESP32 camera control outputs are translated from 3.3 V to 2.8 V; SCCB uses 2.8 V pull-ups. RESET defaults high and PWDN defaults low.
• GPIO mapping: PWDN 17, XCLK 8, VSYNC 6, HREF 4, PCLK 9, D7 2, D6 7, D5 10, D4 14, D3 11, D2 15, D1 13, D0 12.
• SCCB shares the main I2C bus: SCL GPIO16 and SDA GPIO21.
• XCLK target is 20 MHz; include source termination footprints on XCLK and PCLK and low-capacitance ESD where the FPC exposure warrants it.
• Camera rail support must match the selected module pinout. The initial target is a module accepting 3.3 V input and generating sensor sub-rails locally; do not expose raw ESP GPIO to a camera requiring incompatible I/O voltage.

• Main bus: SCL GPIO16, SDA GPIO21, 400 kHz.
• One 2.2 k pull-up pair on the upstream/main bus, selected for the expected connector count and cable capacitance.
• TCA9548A at 0x70 with A0-A2 low.
• Camera SCCB remains upstream of the mux.
• Eight downstream channels each terminate in a four-pin JST-SH Qwiic/STEMMA-QT connector: 3V3, GND, SDA, SCL.
• Firmware scans all eight mux channels and auto-discovers peripherals; ports have no fixed device assignment.
• Expected device addresses include TF-Luna 0x10, BH1750 0x23, VL53L4CD 0x29, focus encoder 0x38, ANO navigation encoder 0x49, optional QMI8658 0x6B, and camera 0x3C upstream.

• Native USB D- GPIO19 and D+ GPIO20.
• USB-C sink-only configuration with independent 5.1 k CC1 and CC2 pull-downs.
• Low-capacitance USB 2.0 ESD array on D+ and D- close to the connector.
• VBUS participates in protected 5 V source ORing.
• USB-only operation is intended for programming and logic bench use; motor VM requires 12 V.

• 12 V inputs: 5.5 x 2.1 mm center-positive barrel jack and parallel XT30 pads.
• Protection order: approximately 3-4 A fuse/PPTC, P-channel MOSFET reverse-polarity stage, then SMBJ-series TVS to motor power ground.
• 12 V to 5 V synchronous buck rated at least 3 A for margin.
• USB 5 V and buck 5 V combined with reverse-current-blocking ideal-diode controllers or suitably rated Schottky ORing if voltage loss remains acceptable.
• 5 V to 3.3 V synchronous buck rated at least 2 A. An LDO is not acceptable at the required peak current because dissipation would be excessive.
• Logic and motor grounds are separate named domains joined at one net-tie/star point near the power entry/buck return. No signal trace may cross the plane split without a controlled return path.

• Field source is a BMS-protected TalentCell-style 12 V battery with separate 12 V and 5 V outputs; this custom board normally derives logic rails from its own protected 12 V input.
• USB-C can power the logic domain without 12 V.
• No battery charging is performed on this board.
• Runtime depends primarily on motor duty cycle and battery capacity and will be validated after motor current and motion profile are measured.

• Four-layer PCB: top signal/component, solid ground reference, power distribution, bottom signal/component.
• Use SMD for high-speed, power-conversion, ESD, and decoupling parts; use through-hole connectors, buttons, electrolytics, and StepStick sockets where practical.
• Prefer components supported by mainstream PCB assembly services, but maintain hand-assembly access for prototype connectors and sockets.
• All connectors require clear pin-1, voltage, polarity, and function silkscreen.
• Motor and power traces/copper must support at least 2 A continuous with margin; exact width and via arrays are set during physical-constraints work.

• Preserve all unchanged r69 GPIO mappings; apply the corrected TFT assignments CS GPIO5 and RST GPIO3 in firmware.
• TMCStepper must use the software-SPI constructor for GPIO43/44/47/48.
• Camera SCCB is on GPIO16/21. A stale comment in the supplied config mentioning GPIO47/48 is not authoritative; the actual defines and r69 pinout use GPIO16/21.
• TCA9548A channels are auto-discovered, so downstream connectors are functionally interchangeable.
• GPIO0 is BOOT-only and has no display or other runtime load.
• GPIO45 is intentionally unused because it is a VDD_SPI strapping pin; do not assign it in firmware.
• UART0 pins GPIO43/44 are repurposed for TMC SPI; debugging uses native USB.
• Onboard touch and onboard IMU are omitted from the custom board. An optional external QMI8658 can use the muxed I2C bus.

• Compact rectangular board with four M3 corner holes.
• Driver socket, VM bulk capacitor, and motor connector grouped at the motor-power edge.
• ESP32 antenna at the opposite board edge with all-layer keepout.
• USB-C, barrel jack, XT30 pads, Qwiic connectors, camera FPC, TFT connectors, and microSD accessible at board edges.
• Place all motor-current loops away from the ESP32 antenna, camera clocks, USB, and logic power conversion.

• Build a custom board that preserves the r69 pinout rather than reproducing the Waveshare carrier mechanically.
• Use separate display/SD and TMC SPI buses as defined by r69.
• Use a 2 A-class 3.3 V buck instead of an LDO.
• Default TMC EN and DIR low to match current firmware.
• Keep camera SCCB and the TCA9548A upstream bus on GPIO16/21.
• Use filtered but non-isolated TMC VIO by default, with an optional isolation footprint for the four SPI lines.

• Camera connector and raw-rail architecture are now fixed to YDS-PAA40-OV5640-1B V1.0 and FH12-24S-0.5SH(55). Module pins D2-D9 form the used 8-bit DVP bus and map in order to firmware CAM_D0-CAM_D7.
• The ST7789 module/FPC pin order will be verified against the selected display before layout.
• USB-C is sink/device only and does not implement USB Power Delivery.
• USB-only operation does not power the stepper motor and may require a high-current USB source for maximum display/camera/SD activity.
• The exact buck-converter, ideal-diode, isolator, TVS, connector, and ESD-array MPNs will be selected from documented library parts during schematic capture.

• Initial specification created from the supplied hardware brief, complete config.h, and ProView LF wiring reference identified internally as r69.
• Resolved the stale camera SCCB comment in config.h: actual pins are SDA GPIO21 and SCL GPIO16.
• Established the fixed r69 TMC software-SPI mapping and exact DVP camera data mapping.
• Added a conservative preliminary power budget and selected a 2 A-class 3.3 V buck architecture.
• Applied the corrected r69 TFT mapping: CS GPIO5 and RST GPIO3; GPIO0 is BOOT-only and GPIO45 is intentionally unused as a VDD_SPI strapping pin. Firmware update required.
• Deferred the camera connector until a specific OV2640 or OV5640 module pinout and rail scheme is selected and verified.