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USB4 High-Speed Layout Constraints and Blockers
Updated: 2026-07-21
Scope
- Inspect current USB4 nets, stackup, ESD layout, and vias.
- Apply supported USB4 net class / skew / impedance metadata.
- Verify GND reference planes and via/ESD constraints; document blockers.
Applied USB4 Net Metadata
Applied/reapplied to all 8 USB4 Gen3/40 Gbps nets:
USB4_TXP0,USB4_TXN0USB4_RXP0,USB4_RXN0USB4_TXP1_CONNECTOR_SIDE,USB4_TXN1_CONNECTOR_SIDEUSB4_RXP1_CONNECTOR_SIDE,USB4_RXN1_CONNECTOR_SIDE
Metadata applied:
Net Type = High SpeedBus Group = USB4_GEN3_40GControlled Impedance = 85 ohmControlled Impedance Pair = USB4_TX0 / USB4_RX0 / USB4_TX1 / USB4_RX1PN Skew Max = 0.1mm
Verification confirmed each USB4 pair resolves to its differential partner.
Stackup / GND Reference Plane Verification
Current stackup is 8 copper layers (
Standard 8 Layer, 1.46 mm total thickness).User decision on 2026-07-21:
- Intended reference-plane assignment is L2 / L4 / L6 as GND planes.
Implementation note:
- Multiple stackup mutation attempts to mark L2/L4/L6 as
Ground Planecaused the stackup readback to collapse to a 4-copper-layer view. - Those failed stackup attempts were reverted to avoid leaving the board in a degraded layer state.
- Current readback is restored to the prior 8-copper-layer stackup, but all copper layers still report as
Signaltype.
Blocker:
- All copper layers currently read as
Signaltype in stackup inspection. - Because the stackup layer types are not marked as
Ground Plane/Power Plane, continuous GND reference planes cannot be proven from metadata yet. - Layout rule options reference names like
L2 Solid GND,L4 Solid GND, andL6 Solid GND, but the actual stackup type readback still shows all copper as Signal.
Recommended next action:
- Do not blindly change the physical stackup without confirming the target PCB manufacturer stackup/impedance calculator.
- Once stackup is confirmed, assign the intended internal GND layers as Ground Plane and verify fills/polygons for uninterrupted return paths under USB4 traces.
Vias / VIPPO / Microvia Verification
Existing via configuration:
- Through-hole only: L1 to L8, 0.6 mm pad / 0.3 mm drill.
- No microvia option is currently exposed in the stackup via configuration.
- No VIPPO-specific via configuration was found.
- GND stitching vias exist, but local stitching density around the final USB4 route cannot be fully verified until the USB4 routes are complete.
Blocker:
- VIPPO/microvias are not currently configured as available routing/via structures.
- Any BGA/USB4 escape strategy requiring VIPPO or laser microvias needs a manufacturer-supported stackup/via definition before final routing.
ESD / USB4 Pass-Through Verification
High-speed ESD parts present:
- D2-D9:
TPD1E0B04DPYT, single-line shunt ESD devices. - All are placed on Top near the USB-C / controller area.
Findings:
- D2-D9 are 2-pin shunt protectors, not true series/pass-through ESD packages.
- Verified USB4 net connectivity currently shows the controller-side nets connected to U1 and the ESD signal pin only.
- J4 USB-C connector high-speed pins are present, but the inspected USB4 nets did not verify as complete J4-to-ESD-to-U1 pass-through connections.
- 2026-07-21 verification: inspecting
J4directly showed its high-speed pins exist, but no nets matched the J4 filter; inspecting the 8 USB4 nets showed only U1 + D2-D9 connections and no J4 connector pins.
Blocker:
- USB4 high-speed connector-side routing/pin-map continuity needs to be resolved before claiming 40 Gbps-ready pass-through layout.
- J2 must remain where the user moved it; if clearance requires J2 movement, ask the user to move it manually.
2026-07-21 J4 continuity repair attempt:
- Confirmed J4 USB4 pins are present but not part of the USB4 nets yet.
- Intended schematic mapping is:
- J4
TX1+::A2->USB4_TXP0 - J4
TX1-::A3->USB4_TXN0 - J4
RX1+::B11->USB4_RXP0 - J4
RX1-::B10->USB4_RXN0 - J4
TX2+::B2->USB4_TXP1_CONNECTOR_SIDE - J4
TX2-::B3->USB4_TXN1_CONNECTOR_SIDE - J4
RX2+::A11->USB4_RXP1_CONNECTOR_SIDE - J4
RX2-::A10->USB4_RXN1_CONNECTOR_SIDE
- J4
- Blocker: schematic connection mutation tool/schema was not available in this run, so the connections were not applied. Do not attempt USB4 PCB routing until these schematic nets include J4.
Current Status
Done:
- USB4 net metadata applied and verified.
- 8-layer stackup confirmed.
- ESD parts identified and placement/layer checked.
- Via capability checked.
Blocked / pending:
- Continuous GND reference plane verification blocked by stackup layer-type metadata.
- VIPPO/microvia verification blocked by via configuration exposing through-hole only.
- USB4 ESD pass-through verification blocked by incomplete/unclear J4 connector-side high-speed net continuity.
Next Safe Steps
- Confirm manufacturer stackup and intended GND/power/signal layer assignment.
- Update stackup layer types only after confirmation.
- Resolve J4 USB4 high-speed pin mapping to U1 through/along D2-D9 ESD shunts.
- Then route USB4 pairs with controlled impedance, matched P/N length, no unnecessary vias, and local GND stitching.
Scope
Applied USB4 Net Metadata
Stackup / GND Reference Plane Verification
Vias / VIPPO / Microvia Verification
ESD / USB4 Pass-Through Verification
Current Status
Next Safe Steps
