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Schematic Capture Preparation — USB4 NVMe SSD Enclosure
Status
Schematic capture is prepared at the block/component-decision level. A simplified ASM2464PD 14-pin placeholder symbol has been imported and can be used for early block wiring, but final ERC/layout remains blocked until the full 273-ball component/footprint is created or the placeholder is expanded.
Imported ASM2464PD placeholder:
Capture Order
  1. USB-C / PD / input protection block
    • USB4 Type-C receptacle
    • USB4 lane ESD
    • CC/SBU ESD
    • USB2 ESD
    • USB-PD sink controller
    • VBUS eFuse / input protection
  2. Power tree block
    • Protected 9 V VBUS from PD/eFuse
    • LM5143 9 V to 3.3 V SSD rail
    • 1.05 V controller core buck
    • 1.9 V controller PHY buck
    • SSD 3.3 V load switch
    • Reset supervisor and power-good/enable sequencing
  3. ASM2464PD controller block
    • Power pins and decoupling
    • REXT 12.1 kΩ
    • 25 MHz crystal and load capacitors
    • SPI flash
    • Reset and strap/configuration pins
    • USB4 lanes to Type-C connector
    • PCIe Gen4 x4 lanes to M.2 socket
    • 100 MHz PCIe REFCLK to M.2 socket
    • PERST# / CLKREQ# / WAKE# / SSD control pins as required by datasheet/reference design
  4. M.2 M-key NVMe socket block
    • PCIe Gen4 x4 TX/RX pairs
    • REFCLK pair
    • PERST#, CLKREQ#, WAKE#
    • SSD_3V3 power pins through load switch
    • Local bulk and high-frequency decoupling
    • Mechanical mounting/standoff constraints
  5. Debug/test block
    • Power rail test points: VBUS_RAW, VBUS_PROT_9V, SSD_3V3, 1V9, 1V05, 3V3_LOGIC, RESET#
    • Optional I2C/UART/debug headers only if ASM2464PD reference design exposes them safely
Selected Component Checklist

Table

FunctionCandidateFlux UID / Status
Main bridge/controllerASM2464PDCustom component required
USB-C receptacleAmphenol ICC 12402060E512A293cc065-6193-43e2-9b90-8eac4a3f4667
USB-PD sinkSTUSB4500QTRc248a604-72c1-48d7-95f5-771d8bab2a00
VBUS eFuse/input protectionTPS259474LRPWR32be918e-7002-499f-9676-a33c5612279f preferred library entry
USB4 high-speed ESDTI TPD1E0B04 family06fd8fee-cf53-42fb-96cc-b44e0b6de189, 902c5128-37bb-4c45-93c4-8060c537c1da, or f9a55989-5f95-4d82-ae7f-ee4cd17456f4
CC/SBU ESDESD224DQA0409994c-c1d8-4441-af3c-8981435c9452
USB2 D+/D- ESDUSBLC6-2SC67b36beaf-0f82-4dc4-82ec-b684d621a657
SSD_3V3 buck controllerLM5143RHAR2176be5d-4a6a-4c66-8881-03f60a39383d
LM5143 MOSFETsCSD17578Q5A7119d0d2-7c83-4a91-9480-58403f3a3e79
LM5143 inductorIHLP2525CZER3R3M012869658a-95e6-47b7-b8fd-5e6eac9dbfe2
LM5143 current senseHoJLR2512-3W-10mR-1%2353a900-0886-4e75-b1b4-6737f693e9a3
LM5143 bootstrap diodeSS140f92afe1-1d1f-0939-c021-d9acab32e4b2
LM5143 input MLCCCL21B106KAYQNNE, 10 µF 25 V X7R 08051d651f64-b02e-4967-bf36-f52f1dd874f3
SSD rail bulk capTCJB107M006R0055, 100 µF 6.3 V polymera55224cd-e7ae-41dc-81d9-54296bc74189
SSD output MLCCs22 µF 10 V X7RUse generic capacitors or add exact MPN
1.05 V buckLMR33630BDDAR6c0ac2ea-01af-431a-9ffd-c6687d52383b
1.9 V buckTPS62901QRYTRQ13bd5c2b9-2cb9-4426-8194-912deee506c4
SSD load switchTPS22995RZGRa6eed642-804f-46a3-b38a-edc108011d78
SPI flashW25Q64JVSSIQ-TR3d52b2e1-2c3c-4eb6-a02d-1389ce111cb8
Reset supervisorTPS3839G33DBZT11077811-d20e-4f81-b52f-4a1bc04ed457
25 MHz crystalExact 16 pF part still missingECS-250-18-23A-EN-TR a43568ed-b67c-4780-b00c-946780032a08 is 18 pF near substitute
M.2 M-key socket91302-67-067R2M777ee2c6-be66-4531-bb48-d0b326b3f6b9
Latest Attachment Additions — Pending Datasheet Confirmation
Crystal / oscillator network
The attachment recommends TXC 7M-25.000MAAJ-T as a 25 MHz / 16 pF / ±30 ppm crystal and recommends 27 pF or 30 pF C0G/NP0 load capacitors for a 16 pF crystal assuming about 2 pF stray capacitance.
Flux library check found:
  • TXC 7M-25.000MAAJ-T, UID 9378a728-f3f0-4df7-8242-10dc6b0d71c7, but the Flux metadata and web/distributor checks say 18 pF, not 16 pF.
  • CC0402JRNPO9BN270, UID d3c01434-cb36-4413-a176-b37e6a633ace, 27 pF C0G/NP0 0402.
Decision:
  • Do not use TXC 7M-25.000MAAJ-T as the exact 16 pF crystal. TXC ordering-code references indicate J = 18 pF; the likely 16 pF ordering code would use I, for example 7M-25.000MAAI-T, subject to availability/confirmation.
  • If the final crystal is truly 16 pF, use 27 pF C0G/NP0 load capacitors as the first-pass value and tune after measuring oscillator margin.
Latest search update:
  • Exact TXC 7M-25.000MAAI-T was not found in Flux; search still resolved to the 18 pF MAAJ part.
  • Exact Epson X1E000021013400 was not found in Flux.
  • Missing-part requests were submitted for both exact crystal candidates.
  • A Flux-available 30 pF C0G/NP0 0402 load capacitor exists: Murata GJM1555C1H300JB01D, UID df387ed0-1f65-4643-83c9-7af95c704f46.
Updated crystal-load decision:
  • For a confirmed 16 pF crystal and estimated 1.5 pF stray capacitance, use 30 pF C0G/NP0 0402 load capacitors as first-pass values.
  • Keep the crystal itself blocked until an exact 16 pF part is added/imported.
TPS259474 first-pass settings
Attachment-proposed settings for the 9 V VBUS eFuse are useful as schematic placeholders:
  • Current-limit resistor: 464 Ω, targeting about 2.6 A if the formula RILIM = 1200 / IOL applies to the selected TPS259474 variant.
  • dV/dt capacitor: 220 pF, targeting about 2 ms ramp with ~22 µF downstream input capacitance.
  • OVLO divider: 768 kΩ top / 100 kΩ bottom, targeting about 10.4 V cutoff if the internal OV threshold is 1.2 V.
Flux resistor availability notes:
  • Exact 464 Ω 1% was not found; 470 Ω 1% 0603 exists (2d1a4674-99d6-4d6a-979f-3bd2d64c30ea) and is about +1.3% from 464 Ω. Prefer exact generic 464 Ω if available during schematic capture; otherwise recalculate current limit with 470 Ω.
  • 768 kΩ 1% exists as CRCW1206768KFKEA, UID 67ca93ea-74c7-4f2a-b9da-736a2c560782.
Decision:
  • Treat these as first-pass placeholders until checked against the TPS259474 datasheet equations and exact variant behavior.
LM5143 compensation placeholder
Attachment-proposed Type-II compensation values:
  • Rc = 3.3 kΩ
  • Cc2 = 4.7 nF
  • Cc1 = 220 pF
Flux candidates:
  • Cc2: GRM155R71E472KA01D, UID 6f6ec781-dbe0-4b5b-a979-a97c44b5a7de.
  • Cc1: CC0402JRNPO9BN221, UID a0b82d2a-b473-4c4e-8bed-4d0d8a82da74.
  • Rc: exact 3.32 kΩ 1% was not found; use generic 3.32 kΩ if available or recalculate with the nearest available value during LM5143 calculator validation.
Decision:
  • Treat these as first-pass calculator placeholders only. Final values must come from the LM5143 calculator using the selected MOSFETs, IHLP2525CZER3R3M01 inductor, actual output capacitance/ESR, and 400 kHz switching frequency.
LM5143 Threshold Verification
Official TI data confirms:
  • EN1/EN2 logic high threshold: 2.0 V
  • EN1/EN2 logic low threshold: 0.8 V
  • TI text also states shutdown when EN is pulled below 0.4 V
Design implication:
  • The 54.9 kΩ / 20.0 kΩ divider gives ~7.49 V rising enable, which is correct for keeping the buck off during 5 V attach.
  • The falling disable point should be treated conservatively: the divider gives ~3.00 V at the 0.8 V low threshold, but guaranteed shutdown wording may require EN <0.4 V, equivalent to ~1.50 V VBUS with this divider.
  • Therefore this divider is suitable for startup gating after 9 V PD negotiation, but not for precise 9 V brownout supervision.
Pre-Capture Blockers
  1. ASM2464PD full component creation remains the main final-layout blocker, but early schematic capture can proceed with the imported simplified placeholder.
  2. Exact 25 MHz / 16 pF crystal is still missing from Flux; use near substitute only if oscillator load network is recalculated.
  3. LM5143 compensation network still needs final calculator values.
  4. USB4 channel still needs S-parameter validation with the selected connector, ESD, stackup, and route geometry.
  5. STUSB4500 PDO configuration must be defined for 9 V / 2.5 A target and fallback behavior.
Ready-for-Schematic Decision
Proceed with schematic capture using the imported ASM2464PD placeholder for exposed pins, and add the selected support set above. Mark unexposed ASM2464PD pins, exact crystal, final compensation, and the production FC-CSP footprint as follow-up items.
Layout Handoff Requirement
Before 8-layer physical layout:
  • Attach or create the production custom footprint: FC-CSP 273 balls, 10 mm × 10 mm, 0.460 mm pitch.
  • Use HDI/via-in-pad rules with filled/capped microvias.
  • Flag high-speed pads such as PCIe PTXP0/PTXN0 R20/R21 and USB4 TX example pads A2/A3 for capped microvia escape after datasheet verification.
  • Avoid high-speed routing stubs and maintain continuous reference return paths for USB4/PCIe.
Final ERC/Layout Expansion Requirements
The 14-pin placeholder does not expose enough pins for final checks. Before final ERC/layout, expand or replace it so the schematic includes:
  • USB4 lane 1 TX/RX pairs in addition to lane 0.
  • PCIe PTX1–3 and PRX1–3 pairs in addition to lane 0.
  • 100 MHz REFCLKP/REFCLKN to the M.2 socket.
  • All VSS/GNDA ground balls and all VCC_33, VCC_19, and VCC_105 power balls.
  • SPI flash pins, reset, straps, UART/GPIO/debug, and test pins.
  • Explicit hardware-strap decisions for boot/configuration behavior.
Early Schematic Capture Progress
Early schematic capture has started with the imported ASM2464PD placeholder.
Added major support blocks:
  • USB-C receptacle, STUSB4500 PD controller, TPS259474 eFuse, CC/SBU/USB2/USB4 ESD protection.
  • LM5143 SSD_3V3 buck controller with first-pass MOSFETs, 3.3 µH inductor, 10 mΩ shunt, bootstrap diode, UVLO divider, and compensation placeholders.
  • 1.05 V and 1.9 V regulator ICs as block placeholders.
  • SSD load switch, SPI flash, reset supervisor, and M.2 M-key socket.
Wired early nets:
  • VBUS_RAW from USB-C VBUS pins to TPS259474 input.
  • VBUS_PROT_9V from TPS259474 output to downstream regulator inputs and LM5143 input network.
  • GND, 3V3_LOGIC, 1V9, 1V05, BUCK_3V3_PRE_SWITCH, and SSD_3V3 net labels.
  • STUSB4500 CC1/CC2 to USB-C CC pins with ESD protection.
  • USB2 D+/D- connector-side protection.
  • ASM2464PD placeholder USB4 lane 0 TX/RX to USB-C pins through single-line ESD devices.
  • ASM2464PD placeholder PCIe lane 0 pins as labeled nets to future M.2 connections.
  • ASM2464PD XI/XO nets to 30 pF load-cap placeholder capacitors; exact 25 MHz / 16 pF crystal still missing.
  • LM5143 first-pass buck power path and compensation placeholder nets.
Unexposed ASM2464PD pins intentionally flagged:
  • USB4 lane 1 TX/RX.
  • PCIe lanes 1–3 TX/RX.
  • PCIe REFCLKP/REFCLKN.
  • SPI flash pins, reset, HDDPC/SSD power control, full GPIO/strap/test pins.
  • Full power/ground arrays and all decoupling pins.
Important schematic caveats:
  • The current schematic is an early block-capture draft, not final ERC-clean hardware.
  • The 1.05 V and 1.9 V regulator support passives/feedback networks still need completion.
  • M.2 high-speed/control pins are not fully wired because the placeholder only exposes PCIe lane 0 and not the full ASM2464PD pin set.
  • Exact 25 MHz / 16 pF crystal is still not placed; only load caps are present.
Validation Snapshot After Early Capture
Schematic summary after early capture:
  • Major support components are present, including U1 placeholder, USB-C/PD/eFuse, LM5143 buck, support rails, M.2 socket, ESD, SPI flash, and reset supervisor.
  • 39 named nets were created, including VBUS_RAW, VBUS_PROT_9V, BUCK_3V3_PRE_SWITCH, SSD_3V3, USB4 lane 0 nets, PCIe lane 0 placeholder nets, and XI/XO crystal nets.
Expected ERC warnings remain:
  • M.2 connector J2 pins are mostly floating because final PCIe/control/power wiring depends on the full ASM2464PD component.
  • LM5143 unused channel 2 and several configuration/support pins are floating pending final single-channel configuration.
  • D6–D9 USB4 ESD devices are present for future lane coverage but currently floating because the placeholder does not expose all USB4 lanes.
  • U9 reset output is floating until the full ASM2464PD RST# and reset tree are wired.
  • Exact crystal is missing; XI/XO currently only have load-cap placeholders.
Do not treat this stage as ERC-clean. It is an early schematic scaffold for the final component expansion pass.
Follow-up Capture Pass
Additional schematic work completed after initial scaffold:
  • M.2 SSD power pins were connected to SSD_3V3 and common ground pins were connected to GND.
  • M.2 PERST#, CLKREQ#, PEWAKE#, and REFCLK pins were labeled as nets requiring the full ASM2464PD component.
  • PCIe Gen4 differential pair pins were not hard-wired to M.2 connector pins because public pinout references conflict on lane/polarity numbering. Use the official PCIe M.2 Socket 3 / connector datasheet before final wiring.
  • 1.05 V and 1.9 V regulator placeholder inductors/capacitors/feedback resistors were added and wired at block level.
Support-Only Completion Pass With 14-Pin Placeholder
Completed all additional wiring that can be done safely without hidden ASM2464PD pins:
  • USB-C orientation-side high-speed connector pins TX2+/TX2-/RX2+/RX2- were connected to dedicated TPD1E0B04 ESD devices on connector-side placeholder nets: USB4_TXP1_CONNECTOR_SIDE, USB4_TXN1_CONNECTOR_SIDE, USB4_RXP1_CONNECTOR_SIDE, and USB4_RXN1_CONNECTOR_SIDE.
  • SPI flash pins were given explicit placeholder nets: ASM_SPI_CS_N_UNEXPOSED, ASM_SPI_DO_IO1_UNEXPOSED, ASM_SPI_DI_IO0_UNEXPOSED, ASM_SPI_CLK_UNEXPOSED, ASM_SPI_WP_IO2_PULLUP_UNEXPOSED, and ASM_SPI_HOLD_RESET_IO3_PULLUP_UNEXPOSED.
  • Reset supervisor output was labeled ASM2464PD_RST_N_UNEXPOSED.
  • STUSB4500 VDD and VBUS_VS_DISCH were connected to VBUS_RAW for attach/PD sensing before the eFuse.
  • USBLC6-2SC6 VBUS reference was connected to VBUS_RAW.
  • LM5143 VCC_1, VCC_2, VDDA, and bootstrap diode source were tied to the LM5143 bias net; PGND1/PGND2 were tied to GND.
  • LM5143 split gate pins HOL1 and LOL1 were tied to the corresponding high-side and low-side gate nets.
  • Unused extra ESD224DQA channels were marked no-connect.
  • Support/control nets were classified by net type: high-speed USB4 nets, medium-speed USB2 nets, low-speed CC/SBU/SPI/reset/control nets, and power rails.
Final Regulator and PD Configuration Pass
Additional regulator/PD configuration pins were finalized so the support circuitry is as complete as practical without the full ASM2464PD symbol:
  • Added R12 = 100 kΩ, 1%, 0402 as the LM5143 RT timing resistor for the 400 kHz first-pass SSD buck setting.
  • Added C13 = 100 nF, 0402 on LM5143 SS1 for soft-start.
  • Added C14 = 10 nF, 0402 on TPS22995 CT for SSD 3.3 V load-switch slew-rate control.
  • Added C15 = 1 µF, 0402 on STUSB4500 VREG_1V2 and C16 = 1 µF, 0402 on VREG_2V7.
  • Added R13 = 0 Ω from STUSB4500 ADDR0 to GND and R14 = 0 Ω from ADDR1 to GND for default address strapping.
  • Added C17 = 10 nF, 0402 on TPS62901 SS/TR.
  • Connected STUSB4500 VSYS to VBUS_RAW so the PD controller has raw Type-C bus/system sensing.
  • Disabled LM5143 channel 2 by tying EN2 to GND and marking the unused channel-2 switching/control pins as no-connect.
  • Tied LM5143 MODE and DEMB low as first-pass conservative mode straps; verify these mode selections against the final LM5143 calculator/design before release.
  • Tied TPS62901 MODE/_S-CONF_1 and MODE/_S-CONF_2 low as first-pass configuration straps; verify the exact VSET/mode table against the selected output-setting method before release.
  • Marked unused optional status/debug pins as no-connect: eFuse PG/status/timer pins, STUSB4500 status/I2C/debug pins not used in the standalone scaffold, and regulator PG pins not consumed by the placeholder ASM2464PD.
Important caveat:
  • These are schematic-completion choices to close the standalone support scaffold. LM5143 compensation/RT/mode, TPS62901 VSET/mode, TPS259474 timer/current-limit behavior, and STUSB4500 NVM PDO programming still require datasheet/calculator confirmation before production release.
Latest ERC snapshot after this pass:
  • No missing-power errors remain from D11 VBUS, U2 VDD/VBUS sense, or U4 VDDA.
  • Remaining ERC state is warning-only and dominated by expected floating pins from the incomplete ASM2464PD placeholder and M.2 connector.
  • Remaining warnings also include regulator configuration pins that still need final calculator/datasheet decisions, including LM5143 channel-2 disable/config pins, LM5143 SS/RT/MODE/PG/VCCX pins, TPS62901 mode/soft-start/PG pins, LMR33630 PG, TPS259474 status/timer pins, STUSB4500 I2C/address/status/internal regulator pins, and TPS22995 CT.
Remaining hard limitation:
  • The current tools do not expose a way to add terminals to the imported ASM2464PD placeholder. Full 273-ball expansion still requires replacing/reimporting the component with a complete KiCad/Flux part.
Altium Demo Archive Import Result
The uploaded ASM2464PD DEMO Board B2 [Altium Designer].zip was imported and produced a second ASM2464PD part project, but a test insertion exposed no pins. That inspection instance was removed.
Result:
  • The current 14-pin U1 placeholder remains the only usable ASM2464PD schematic component in this project.
  • The Altium archive did not automatically unblock full 273-ball schematic capture.
  • Next best source is a dedicated .SchLib, .PcbLib, .IntLib, or full 273-pin KiCad symbol/footprint pair.
Dedicated SchLib Import Result
The uploaded ASM2464PD.SchLib.zip was imported successfully and produced a new ASM2464PD component project:
Verification action:
  • A temporary test instance U_TEST_FULL was inserted into the enclosure schematic.
  • Inspection showed the imported component exposed no schematic pins/terminals.
  • The test instance was removed to avoid disrupting the existing scaffold.
Result:
  • The dedicated SchLib import did not provide a usable 273-pin ASM2464PD schematic symbol in Flux.
  • Keep the existing 14-pin U1 placeholder for early scaffold wiring.
  • Full ASM2464PD expansion still requires a Flux/KiCad component that exposes all terminals, or manual symbol creation from the verified pin/ball source file.

  • Status

  • Capture Order

  • Selected Component Checklist

  • Latest Attachment Additions — Pending Datasheet Confirmation

  • Crystal / oscillator network

  • TPS259474 first-pass settings

  • LM5143 compensation placeholder

  • LM5143 Threshold Verification

  • Pre-Capture Blockers

  • Ready-for-Schematic Decision

  • Layout Handoff Requirement

  • Final ERC/Layout Expansion Requirements

  • Early Schematic Capture Progress

  • Validation Snapshot After Early Capture

  • Follow-up Capture Pass

  • Support-Only Completion Pass With 14-Pin Placeholder

  • Final Regulator and PD Configuration Pass

  • Altium Demo Archive Import Result

  • Dedicated SchLib Import Result

USB4 NVMe SSD Enclosure

USB4 NVMe SSD Enclosure thumbnail
USB4 external NVMe SSD enclosure PCB targeting an ASM2464PDX-class USB4 40 Gbps device controller with PCIe Gen4 x4 downstream M.2 NVMe interface, USB-C upstream port, power management, ESD protection, and controlled-impedance layout constraints.

Properties

Consumer Electronics

USB4 40 Gbps NVMe enclosure with USB-C PD input, protected VBUS, 3.3 V SSD rail, 1.05 V/1.9 V controller rails, and controlled-impedance layout requirements.

USB

USB

5

V

Bluetooth

Pricing & Availability

Distributor

Qty 1

Arrow

$12.14–$15.67

Digi-Key

$1.04

HQonline

$0.14–$0.35

LCSC

$21.87–$22.11

Mouser

$25.24–$25.32

TME

$1.08

Verical

$6.16–$7.33

Controls