Diagram

• 3 A synchronous adjustable buck regulator.
• Supports 5 V input.
• Output adjustable down to ~1 V class.
• Meets ASM2464PD VDD max current of ~1.812 A with margin.

• PowerSOIC/8-PowerSOIC package, not tiny QFN. Acceptable for prototype, not optimal for compact enclosure.

• 1 A synchronous buck regulator.
• Adjustable output suitable for 1.9 V.
• Current margin over datasheet max VCCL current of ~455.7 mA.
• Compact 9-TFQFN package.

• TI dual synchronous buck controller, not an integrated regulator.
• 3.5–65 V input operating range, so 5 V input to 3.3 V output is valid.
• Output current is set by external MOSFETs, inductor, current sensing, layout, and thermal design; it can support currents above the 4–5 A SSD target when designed correctly.
• Better fit for high-current SSD_3V3 than a 3 A integrated buck.

• Requires external MOSFETs, inductor, compensation/current-sense design, and careful layout. It is more complex than a monolithic buck.

• Suitable for lower-current 3.3 V logic/support rails or a conservative low-power SSD design.
• Not enough margin for the main high-performance M.2 SSD 3.3 V rail target.

• Use LM5143 for the high-current SSD_3V3 rail if we are comfortable with a controller + external MOSFET power stage.
• Do not use TPS62823 or LMR33630 as the final SSD rail for high-performance NVMe drives unless the SSD current limit is intentionally reduced.

• A 3.3 V / 5 A rail is 16.5 W. At 5 V input and ~90% efficiency this would be about 3.7 A from VBUS, before controller rails and losses. Therefore full 5 A SSD margin cannot be guaranteed from a basic 5 V / 3 A USB-C source.
• Full-power mode is now first-pass locked to USB-PD 9 V / 2.5 A. At 9 V and ~90% efficiency, the SSD rail input current is about 2.05 A, leaving more margin under a 3 A cable/source limit while avoiding the higher switching stress of 15 V/20 V conversion.
• 5 V operation should be treated as reduced-power/fallback mode unless a current limit prevents SSD overdraw.

• 0.5–5.5 V input range.
• GPIO enable control.
• Current capability above 4 A.
• Suitable for switching the SSD 3.3 V rail under ASM2464PD HDDPC or equivalent power-control logic.

• MP5036GJ-P, UID acf3789a-d938-4cff-aed3-06bc119974d3, if adjustable current limiting is required.

• 2.7 V to 23 V operating input range supports 5 V attach and 9 V PD operation.
• Integrated back-to-back FETs provide reverse-current blocking.
• Adjustable current limit supports the 9 V / 2.5 A PD power path.
• Provides overvoltage, overcurrent/short-circuit, reverse-current, inrush, and thermal protection features in a compact QFN package.

• Place after USB-C/PD source path and before downstream LM5143/system regulators.
• Set current limit above normal 9 V full-load input current but below unsafe cable/source stress; first-pass target around 3 A, to be finalized from TPS25947 datasheet equations and total system current.
• Use eFuse power-good/fault status if useful for enabling downstream rails or diagnostics.

• Confirm exact TPS259474 variant behavior: clamp/cutoff mode, OVLO/OVC setting, current-limit resistor, dV/dt capacitor, thermal loss at ~2–3 A, and coordination with STUSB4500 gate/control outputs.

• Current limit: RILIM = 464 Ω, target ~2.6 A if RILIM = 1200 / IOL applies.
• Inrush ramp: CdVdt = 220 pF, target ~2 ms ramp with ~22 µF downstream capacitance.
• OVLO divider: 768 kΩ top / 100 kΩ bottom, target ~10.4 V cutoff if the OV threshold is 1.2 V.

• W25Q64JVSSIQ-TR, UID 3d52b2e1-2c3c-4eb6-a02d-1389ce111cb8

• Winbond 64 Mbit SPI/QSPI NOR flash.
• 3.3 V class.
• SOIC-8 package.
• Larger than the initial 8–16 Mbit request, but likely acceptable if ASM2464PD ROM boot supports it.

• Confirm exact SPI flash density and vendor support from ASMedia reference design or firmware package.

• 25 MHz
• ±30 ppm long-term stability at 25 °C
• ±30 ppm temperature stability
• 16 pF single-ended load capacitance

• ECS-250-18-23A-EN-TR, UID a43568ed-b67c-4780-b00c-946780032a08
• 25 MHz, ±30 ppm, 18 pF load capacitance, SMD

• Use only as a near substitute if the crystal load network is recalculated and validated.
• Prefer an exact 25 MHz / 16 pF / ±30 ppm SMD crystal when available.
• No exact 16 pF Flux part was found in the latest search; keep the 18 pF ECS part as a near substitute only.
• Latest crystal correction: TXC 7M-25.000MAAJ-T is also 18 pF, not 16 pF. TXC ordering-code references indicate the J load-capacitance code is 18 pF; the likely 16 pF variant would use I, for example 7M-25.000MAAI-T, subject to distributor/manufacturer confirmation. Do not use 7M-25.000MAAJ-T as the exact 16 pF solution.
• Latest Flux search: exact TXC 7M-25.000MAAI-T and Epson X1E000021013400 were not found in Flux; missing-part requests were submitted for both. For a confirmed 16 pF crystal, first-pass load capacitors are 30 pF C0G/NP0 0402, using Murata GJM1555C1H300JB01D, UID df387ed0-1f65-4643-83c9-7af95c704f46.

• 3.3 V voltage supervisor.
• Active-low reset output.
• Suitable for driving/conditioning ASM2464PD RST#.

• Confirm reset timing against the ASM2464PD power-on sequence and regulator power-good timing.

• 12.1 kΩ ±1% resistor from REXT pin per datasheet.

• Generic Resistor UID b67f50a9-ae5e-10ea-9c3c-d377e2ab3b2d
• Value: 12.1 kΩ
• Tolerance: 1%
• Package: 0402 or 0603 depending assembly preference

• For USB4/SuperSpeed pins, do not use multi-line/port TVS/ESD packages to minimize crosstalk.

• Reject 10 Gbps-only multi-line ESD arrays for USB4 lanes.
• Do not use PESD4USB3U-TTSX or TPD4E02B04 on the USB4 40 Gbps high-speed lanes. They may still be considered for lower-speed lines such as USB2, CC, SBU, or control lines if their voltage/capacitance ratings fit.
• Prefer single-line or extremely low-parasitic lane-local protection with published S-parameter data or vendor-provided RF models.

• TPD1E0B04DPYT, UID 06fd8fee-cf53-42fb-96cc-b44e0b6de189, X1SON-2
• TPD1E0B04DPYR, UID 902c5128-37bb-4c45-93c4-8060c537c1da, X1SON-2
• TPD1E0B04DPLT, UID f9a55989-5f95-4d82-ae7f-ee4cd17456f4, X2SON-2

• TI positions it for USB Type-C, USB4, Thunderbolt 4, and high-speed interfaces up to 60 Gbps.
• Typical capacitance is ~0.13 pF.
• TI lists >30 GHz -3 dB bandwidth and insertion-loss plots to 40 GHz in the datasheet.
• TI product page lists a downloadable TPD1E0B04 S-Parameter Model.
• Single-channel device aligns better with the ASM2464PD warning against multi-line/port ESD packages.

• Use one TPD1E0B04 per high-speed conductor, placed immediately behind the USB-C connector with the shortest possible ESD return path to chassis/ground reference.
• For four USB4 differential pairs at the USB-C receptacle, budget 8 single-line ESD devices unless the final reference design specifies a different topology.

• Nexperia positions PESD2V8R1BSF for USB4 and Thunderbolt interfaces.
• Reported RF figures include approximately -0.21 dB insertion loss at 10 GHz and -17.4 dB return loss at 10 GHz.
• Ultra-low capacitance, approximately 0.1 pF class.

• Confirm access to Touchstone/S-parameter model or Nexperia RF support package before using it as the final production selection.

• Nexperia explicitly targets these newer TrEOS devices at USB4 and Thunderbolt.
• Public material claims insertion loss down to about -0.21 dB at 12.8 GHz and no resonance up to 40 GHz.
• RF and SEED simulation models are available from Nexperia/design support.

• Exact 1 V variants should be added/imported if chosen.
• Verify working voltage compatibility with the ASM2464PD USB4 AC-coupled high-speed pins and ESD clamping needs.

• Semtech’s USB4 guidance lists approximately 0.17 pF line-to-line capacitance, -0.25 dB insertion loss at 10 GHz, and -22 dB return loss at 10 GHz.

• Need exact part import and direct datasheet/S-parameter model access before final use.

• Flux library part exists.
• ST describes it as a common-mode filter with ESD protection for high-speed interfaces including USB4.
• Datasheet lists 10.7 GHz differential bandwidth.
• Related ST variants have public S-parameter model downloads.

• This is not a simple TVS diode; it is an inline common-mode filter + ESD element, so it adds series path discontinuity and loss.
• Use only if full channel simulation shows margin. For maximum NVMe performance, prefer a single-line TVS solution first.

• TI TPS25750-class USB-PD controller if firmware/configuration flexibility is required and a suitable Flux part/library source is available.

• Use fixed 5 V sink behavior only for reduced-power prototypes or compatibility mode.
• For the full 3.3 V / 5 A SSD rail target, request 9 V / 2.5 A as the target PD object.
• Configure the LM5143 UVLO so SSD_3V3 remains off during the initial 5 V attach/handshake and turns on only after successful 9 V negotiation; first-pass UVLO turn-on target is about 7.5 V.
• Locked LM5143 UVLO divider, using nominal 2.0 V rising / 0.8 V falling EN thresholds: RUV1 = 54.9 kΩ top from VBUS to EN, RUV2 = 20.0 kΩ bottom from EN to GND. This gives approximately 7.49 V rising turn-on and 3.00 V falling shutdown. The low falling threshold prevents nuisance trips during 9 V transients, but it is not a tight 9 V brownout cutoff.

• PDO1: 5 V fallback / low-current compatibility.
• PDO2: 9 V / 2.5 A target object, highest priority for full-power mode.

• Obtain/download S-parameter models for the chosen ESD device.
• Include the USB-C connector, ESD pads, vias/escapes, ASM2464PD package escape, stackup, and route geometry in the channel-loss review.
• Confirm no excessive insertion loss, return loss, or crosstalk at the USB4 Gen3 40 Gbps operating region.

1. ASM2464PD custom component
2. LM5143 calculator/thermal validation and final compensation network
3. Final USB4 single-line ESD variant after S-parameter/channel review
4. Exact 25 MHz / 16 pF crystal
5. Verify LM5143/TPS259474 calculator values, compensation, and thermal margins; add/import exact 25 MHz / 16 pF crystal; define reduced-power behavior for non-PD 5 V sources