The independent review caught several unsafe issues in the first implementation, so I’m correcting them before closing: overvoltage on U3 EN/UVLO, TPS65987D dead-battery boot strapping, unsuitable TVS selection, and the connector’s 20 Gbps limitation.
Work is paused because no ACUs are currently available, so I could not retrieve or verify the executor’s final correction report.
Completed before the pause: J4 connectivity, a TPS65987D-based PD block, protected ASM VBUS sensing, a 100 × 80 mm board resize, and an independent safety review. Still requiring confirmation are the corrected U3 EN/UVLO network, TPS65987D dead-battery boot, PD-rated TVS, true 40 Gbps J4 replacement, ≥4 A SSD switch, duplicate U10 removal, and M.2 keepout.
Use a standard 3.3 µH inductor as the first-pass 9 V / 400 kHz selection.
The earlier 2.1 MHz / 0.68 µH option is downgraded to compact-experiment status only; it is likely hotter and harder to validate thermally in an enclosure.
Final FSW/inductor must still be confirmed with the LM5143 calculator and thermal estimates.
Ripple estimate at VIN = 9 V, VOUT = 3.3 V, L = 3.3 µH, FSW = 400 kHz:
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ΔIL = VOUT / (L * FSW) * (1 - VOUT/VIN)
ΔIL ≈ 3.3 / (3.3 µH * 400 kHz) * (1 - 3.3/9)
ΔIL ≈ 1.58 A p-p
Peak inductor current at 5 A load ≈ 5.79 A
Attachment-reported saturation current is 13.5 A, above the preferred >=8 A target.
Compact 6.5 mm × 6.5 mm IHLP-2525 footprint and ~3.0 mm profile.
Acceptable first-pass DCR class for the 5 A SSD rail, though thermal rise must still be checked.
Preferred-if-imported candidate from attachment:
Coilcraft XAL5030-332MEC, target 3.3 µH, attachment-reported Isat 8.7 A, Irms 8.1 A, DCR 21.2 mΩ typ / 23.3 mΩ max.
Flux search did not find exact XAL5030-332MEC; it returned XAL4030-332MEC (9605980b-7638-4688-bd14-758b2fa86099), which is only 6.6 A / 28.6 mΩ max and is marginal against the preferred >=8 A target. Do not substitute XAL4030 without thermal/current-margin review.
Previous selected 0.68 µH candidate is no longer the first-pass full-power inductor:
10 mΩ gives approximate current-limit peak of 73 mV / 10 mΩ = 7.3 A.
Subtracting half-ripple gives ~6.5 A output-current trip estimate with the 9 V / 3.3 µH / 400 kHz design, providing margin above 5 A load.
2512 / 3 W option preferred for low thermal rise and Kelvin routing margin.
Validation required:
Verify LM5143 current-limit tolerance, blanking/min on-time, and sense-filter requirements.
Kelvin-route shunt sense lines directly to CS/VOUT pins.
Output Capacitors
First-pass requirement:
Use low-ESR ceramic + bulk capacitance near the SSD load switch and M.2 connector.
Suggested starting point: 2–4 × 22 µF, 6.3 V or 10 V X7R MLCC near regulator output plus 47–100 µF polymer/bulk near SSD rail.
Validation required:
Account for MLCC DC-bias derating.
Confirm LM5143 loop stability and output ripple with actual capacitor ESR/ESL.
Loop-compensation starting point:
For the 400 kHz design, target crossover around 40 kHz, roughly 1/10 switching frequency.
Place the Type-II compensation zero near/slightly below the output filter pole and target phase margin above 60 degrees.
Exact COMP resistor/capacitor values must be calculated from the final LM5143 configuration, modulator gain, current-sense method, output capacitance, ESR, chosen FSW, and final 3.3 µH inductor.
UVLO / Startup
First-pass full-power behavior:
Configure LM5143 UVLO so SSD_3V3 remains off during initial 5 V USB-C attach/PD negotiation.
Set UVLO turn-on around 7.5 V so the buck starts only after the PD controller successfully negotiates 9 V.
Provide a reduced-power/fallback mode separately if the product must run from non-PD 5 V sources.
Locked first-pass UVLO divider using LM5143 EN thresholds from the latest validation note:
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VEN = VBUS * RUV2 / (RUV1 + RUV2)
Target: VEN = 2.0 V at VBUS = 7.5 V
Choose RUV2 = 20.0 kΩ
RUV1/RUV2 = (7.5 - 2.0) / 2.0 = 2.75
RUV1 = 55.0 kΩ ideal
Use RUV1 = 54.9 kΩ, RUV2 = 20.0 kΩ, 1%
Result with 54.9 kΩ / 20.0 kΩ:
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VBUS_START ≈ 2.0 V * (54.9 kΩ + 20.0 kΩ) / 20.0 kΩ = 7.49 V
VBUS_STOP ≈ 0.8 V * (54.9 kΩ + 20.0 kΩ) / 20.0 kΩ = 3.00 V
VBUS_FORCED_SHUTDOWN_TEXT ≈ 0.4 V * (54.9 kΩ + 20.0 kΩ) / 20.0 kΩ = 1.50 V
Decision:
Lock RUV1 = 54.9 kΩ top and RUV2 = 20.0 kΩ bottom as the schematic values.
Rising turn-on at ~7.49 V keeps the SSD buck disabled during the initial 5 V USB-C attach/PD negotiation phase.
Datasheet verification nuance: TI lists EN low threshold as 0.8 V and EN high threshold as 2.0 V, but the feature text also says shutdown occurs when EN is pulled below 0.4 V. Treat the 7.49 V rising enable as valid for startup gating. Treat the falling point conservatively; this divider is not a tight 9 V brownout cutoff. If the final product needs tighter 9 V input supervision, add a separate supervisor or use PD-controller power-good gating.
Validation required:
Confirm final part variant threshold tolerances and EN leakage in the datasheet, but the nominal divider values are locked for schematic capture as a startup-gating network.
Use generic 1% resistors for the UVLO divider unless exact resistor MPNs are required.
Input MLCCs: CL21B106KAYQNNE, 10 µF / 25 V / X7R / 0805, UID 1d651f64-b02e-4967-bf36-f52f1dd874f3; use at least two close to the high-side FET drain/current loop.
Output MLCCs: use generic 22 µF / 10 V / X7R capacitors unless an exact MPN is added; no exact Flux library part was found in the requested 0805/1206 class.
UVLO resistors: generic 54.9 kΩ 1% top and 20.0 kΩ 1% bottom.
Compensation network:
Use generic passives initially.
Final values must come from the LM5143 calculator after finalizing output capacitance, ESR, inductor DCR, MOSFETs, and switching frequency.
Latest attachment-proposed placeholders: Rc = 3.3 kΩ, Cc2 = 4.7 nF, Cc1 = 220 pF. Use these only as schematic placeholders until the LM5143 calculator confirms stability.
Flux-available capacitor candidates for placeholders: