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ASM2464PDX Replacement Report
Source
User-uploaded PDF:
rFxysghQIA4PsgmCFdVR0jBjYuY21pitWd0yOoS9.pdf.The PDF identifies the device as ASM2464PDX, not plain ASM2464PD.
Extracted package facts:
- Manufacturer: ASMedia
- Function: USB4/Thunderbolt to PCIe Gen4 x4 controller for multi-PCIe / NVMe devices
- Package: 10 mm × 10 mm FCCSP / FC-CSP
- Ball count: 273
- Ball pitch: 0.460 mm
- Nominal ball diameter: 0.230 mm
- Ball width range: 0.170–0.270 mm
Action taken
Replaced the previous 14-pin
U1 ASM2464PD placeholder with a newly created ASM2464PDX component derived from the uploaded PDF.The new U1 exposes the key functional pins used in this project:
- USB4 lane 0:
UTXP0,UTXN0,URXP0,URXN0 - PCIe lane 0:
PTXP0,PTXN0,PRXP0,PRXN0 - Crystal:
XI,XO - Power:
VDD_GROUP,VCCL_GROUP,VCCH_GROUP,VCCA33 - Ground:
GND_GROUP,GNDA_GROUP - USB-C sideband/power pins:
VBUS,CC1,CC2,SBU1,SBU2 - PCIe refclks, resets, SPI, UART, GPIO, and control pins from the PDF table
Net remapping performed
Table
| Old placeholder intent | New ASM2464PDX pin | Net |
|---|---|---|
VCC_105 | VDD_GROUP | 1V05 |
VCC_19 | VCCL_GROUP | 1V9 |
VCC_33 | VCCH_GROUP, VCCA33 | 3V3_LOGIC |
VSS | GND_GROUP, GNDA_GROUP | GND |
U4_TXP0 | UTXP0 | USB4_TXP0 |
U4_TXN0 | UTXN0 | USB4_TXN0 |
U4_RXP0 | URXP0 | USB4_RXP0 |
U4_RXN0 | URXN0 | USB4_RXN0 |
PTXP0 | PTXP0 | PCIE_TXP0_TO_M2 |
PTXN0 | PTXN0 | PCIE_TXN0_TO_M2 |
PRXP0 | PRXP0 | PCIE_RXP0_FROM_M2 |
PRXN0 | PRXN0 | PCIE_RXN0_FROM_M2 |
XI_25M | XI | XI_25M |
XO_25M | XO | XO_25M |
Placement
U1 was placed on the PCB between the USB-C connector (
J1) and M.2 connector (J2). Nearby crystal/load caps and USB4 ESD parts were adjusted to clear the larger 10×10 mm FCCSP package.Important limitations
The Flux component currently groups the many repeated power, ground, and NC balls into grouped schematic terminals:
VDD_GROUPVCCL_GROUPVCCH_GROUPGND_GROUPGNDA_GROUPNC_GROUP
This is acceptable for schematic intent capture, but it is not yet a production-grade 273-ball symbol/footprint representation. Before final PCB routing/manufacturing, these grouped pins should be expanded to individual balls and verified against the official datasheet or vendor CAD library.
Current ERC warnings are expected because many newly exposed ASM2464PDX pins are not yet wired: USB4 lane 1, PCIe lanes 1–3, refclks, CC/SBU/VBUS, SPI, reset, GPIO straps, and sideband signals need intentional wiring or no-connect treatment.
Next recommended work
- Wire CC1/CC2/SBU/VBUS from U1 to the Type-C/PD/protection block as appropriate.
- Wire SPI flash pins (
SPI_CS#,SPI_DO,SPI_DI,SPI_CLK) toU8. - Wire reset/control pins (
RST#,HDDPC,PERST0#,GPIO8/CLKREQ#, etc.) to the intended supervisor/M.2 control nets. - Decide whether this design uses only PCIe x4 to one NVMe device or multiple PCIe ports, then wire all relevant PCIe lanes/refclks.
- Expand grouped power/ground pins into individual balls before final PCB routing.
- Re-run ERC, then place/reroute with high-speed differential constraints.
Source
Action taken
Net remapping performed
Placement
Important limitations
Next recommended work
