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ASM2464PDX New PDF and Reference Schematic Comparison
Date: 2026-07-08
Sources reviewed:
  • ASM2464PDX_DataSheet_unlocked (1).pdf
  • ASM2464PDX_TI_R03.pdf
  • Current project schematic and ERC/DRC state
Executive Summary
The new PDFs materially change the confidence level and the required follow-up work. The unlocked datasheet is PDX-specific and confirms that the current U1 pin model is broadly aligned with the 273-ball ASM2464PDX pinout and rail naming, but the reference schematic shows several support circuits that are still missing or architecturally different in this project.
The current design should not be treated as a near-final ASM2464PDX implementation yet. The largest blockers are the USB-C/PD/CC architecture, missing VBUS sense, missing REXT, incomplete 25 MHz crystal circuit, M.2 connector/keying cleanup, and final PCIe sideband validation.
What the New Datasheet Confirmed

Table

AreaPDF FindingCurrent Design StatusImpact
Device/packageASM2464PDX, USB4/TBT to PCIe Gen4 x4, 10 mm x 10 mm FCCSP, 0.46 mm pitch, 273 ballsU1 is ASM2464PDX and now exposes individual ball-style terminals in the schematicPositive: current U1 is much closer than earlier grouped-pin notes suggested
Power railsVCCH 3.3 V, VCCA33 3.3 V analog, VCCL 1.9 V, VDD 1.05 VU1 VCCH/VCCA33 -> 3V3_LOGIC; VCCL -> 1V9; VDD -> 1V05; GND/GNDA -> GNDMostly aligned
Power sequenceVBUS/5 V -> VCCH within 3-6 ms; VCCL after VCCH; VDD within 90 ms; reset/clock/refclk sequencing called outRails exist, but regulator placeholder nets remain and sequencing has not been fully auditedNeeds power-tree/sequencing review
REXTREXT requires 12.1 kΩ ±1%ASM_REXT_12K1_REQUIRED has only U1 connectedMissing required resistor
Clock25 MHz crystal; CL 16 pF single-ended; differential CX 10 pF / CTOTAL 9-15 pFXI_25M and XO_25M each only have U1 plus a 30 pF capacitor; no crystal component foundMissing crystal, load caps likely need recalculation
USB4 ESDDo not use multi-line/port TVS packages on USB high-speed pinsUSB4 conductors use one TPD1E0B04DPYT per conductorDirectionally aligned; still needs high-speed insertion-loss/placement validation
PCIe x4 sidebandsx4 mapping uses REFCLK0, GPIO8/CLKREQ#, PERST0#, GPIO22/PE_WAKE#, GPIO2/PRSNT#/INS#REFCLK0, GPIO8, PERST0#, GPIO22 are present; GPIO2/PRSNT appears not connectedGPIO2 presence-detect needs follow-up
USB-C CC/PDASM includes CC logic/BMC and supports PD sink / USB4/TBT discovery; external PD controller can be supported via I2CCurrent connector CC is owned by STUSB4500, U1 CC pins are DNP placeholdersMajor architecture mismatch
What the Reference Schematic Adds
The reference schematic PDF appears to use a TI TPS65988DK-style external PD controller for ASM2464PDX, not an STUSB4500-only CC sink controller. It shows/reference-notes:
  • USE TPS65988DKRSHR External PD for ASM2464PDX.
  • CC nets CC1_C / CC2_C associated with the ASM and the external PDC path.
  • I2C/interrupt/reset-style links between the ASM and the PDC, including nets resembling I2C_DATA_P1, I2C_CLK_P1, GPIO1 / I2C_INT_PDC, RST, and GPIO26.
  • One-line 0201 USB4 ESD recommendation, noted as ESD150-B1-W0201 for USB4 Gen3 near the Type-C connector.
  • REXT implemented as 12.1 kΩ 1%.
  • 25 MHz crystal close to XI/XO, with explicit layout note: XI/XO as short as possible and XTAL caps as 0402 NP0/C0G.
  • PCIe x4 sideband nets for REFCLK, CLKREQ, PERST, PE_WAKE, and presence signals.
OCR quality is imperfect, so exact resistor/capacitor values from dense schematic areas should be rechecked visually before mutation.
Current Schematic Findings
Good / confirmed
  • U1 is an ASM2464PDX with individual ball terminals and the pin list matches the new PDX datasheet much better than prior ASM2464PD-only assumptions.
  • Power rails are connected to the expected rail names:
    • 3V3_LOGIC -> VCCH and VCCA33
    • 1V9 -> VCCL
    • 1V05 -> VDD
    • GND -> GND/GNDA
  • USB4 high-speed ESD is implemented as individual single-line parts (D2-D9, TPD1E0B04DPYT), which is consistent with the datasheet warning to avoid multi-line TVS packages.
  • SPI flash nets exist between U1 and U8.
  • Reset supervisor net exists between U1 RST# and U9.
  • M.2/PCIe sideband nets exist for REFCLK0, CLKREQ, PERST0#, and PE_WAKE.
Needs change / incomplete
  1. PD / CC architecture
    • Current U2 is STUSB4500QTR.
    • Connector CC nets are J1 -> U2 -> ESD, while U1:CC1 and U1:CC2 remain on ASM_CC1_POLICY_PENDING_DNP / ASM_CC2_POLICY_PENDING_DNP.
    • U2 SCL / SDA are not part of a meaningful ASM/PDC control scheme in the inspected schematic.
    • Reference schematic uses a TPS65988DK-style external PDC for ASM2464PDX.
    • This is the biggest material change: STUSB4500 is likely not equivalent for USB4/TBT discovery and ASM coordination.
  2. U1 VBUS sense
    • ASM_VBUS_SENSE_PENDING_DIVIDER has only U1:VBUS connected.
    • The PDF confirms U1 VBUS is 5 V tolerant, while this design can negotiate around 9 V.
    • Need a real, 5 V-safe VBUS sense/protection path from the appropriate connector/bus node.
  3. REXT
    • ASM_REXT_12K1_REQUIRED has only U1:UREXT connected.
    • Add 12.1 kΩ ±1% to the required reference node, expected GND unless the final visual schematic review shows otherwise.
  4. 25 MHz clock
    • XI_25M: U1:XI + C7 30 pF only.
    • XO_25M: U1:XO + C8 30 pF only.
    • No crystal/resonator component found between XI and XO.
    • Add a 25 MHz crystal and recalculate load capacitors from the selected crystal CL and PCB/pin stray capacitance. The current 30 pF caps look suspect.
  5. PCIe presence and connector cleanup
    • For single x4 NVMe, datasheet mapping expects GPIO2 as PRSNT#/INS#.
    • Current GPIO2 presence function was not found connected.
    • Project summary still shows an M.2 Key B Connector (U10) while the active renamed M.2 connector appears to be J2. For an NVMe M-key target, remove/replace any wrong or duplicate connector symbols and verify the exact M-key pinout.
  6. SPI flash details
    • SPI flash signals are present, but WP/HOLD/RESET-style nets are still placeholder-named.
    • Confirm pullups, voltage domain, programming access, and boot strap interactions.
  7. Power tree / sequencing / decoupling
    • Several regulator nets still have placeholder-style names (LM5143_FB1_COMP_PLACEHOLDER, U5_BOOT_PLACEHOLDER, U6_FB_VSET_PLACEHOLDER, U6_FB_VSET2_PLACEHOLDER).
    • The reference schematic includes many local decoupling capacitors around the ASM. Current decoupling should be audited against rail count and BGA placement before layout.
Prioritized Next Actions
  1. Decide and implement the ASM2464PDX USB-C/PD architecture:
    • Either replace STUSB4500 with a TPS65988DK-class external PDC flow matching the reference schematic, or prove an ASM-internal PD/CC mode is sufficient for the target product.
  2. Add the 25 MHz crystal and correct load-cap network.
  3. Add the 12.1 kΩ ±1% REXT resistor.
  4. Add a 5 V-safe U1 VBUS sense/protection network.
  5. Verify and fix M.2 connector/keying and connect GPIO2 PRSNT#/INS# if required.
  6. Audit SPI flash pullups/straps, reset timing, rail sequencing, and decoupling.
  7. Re-run ERC/DRC and separate expected placeholder warnings from real missing support circuitry.
Bottom Line
Yes, the new PDFs changed the assessment. The U1 pinout/rail model is now better supported by a PDX-specific source, but the reference schematic exposes several missing required support circuits and a likely PD/CC architecture mismatch. Treat this as a schematic-correction phase before continuing layout/routing.
2026-07-08 Update: Option A Selected
The user selected Option A: standard bus-powered 5 V enclosure using ASM2464PDX internal CC/BMC/PD capability.
Changes applied:
  • Removed the external TPS65988DKRSHR path (U11) and its local support capacitors (C901, C902, C903).
  • Removed the deprecated STUSB4500 path and its immediate support passives (U2, C15, C16, R13, R14).
  • Re-added J1 as the upstream USB-C receptacle.
  • Reconnected J1 USB4, USB2, SBU, VBUS, ground/shield, and CC nets.
  • Kept J1:CC1 / J1:CC2 connected to U1:CC1 / U1:CC2, so ASM2464PDX owns Type-C attach/orientation and fixed-5 V sink behavior.
  • Connected U1:VBUS and U3:EN/UVLO to VBUS_RAW for the first-pass 5 V bus-powered path.
  • Removed stale external-PDC I2C/IRQ connections from U1:I2C_CLK_P, U1:I2C_DATA_P, and U1:GPIO1 and marked those pins intentionally unused for this architecture.
Verification notes:
  • No U11-related ERC checks remain because U11 was removed.
  • No J1 or U3 ERC checks were reported after the rework.
  • USB_C_CC1 and USB_C_CC2 now contain J1, U1, and the ESD device only.
Remaining open items for Option A:
  • Confirm from ASMedia collateral/reference design that directly tying U1:VBUS to 5 V VBUS_RAW is preferred for the final fixed-5 V bus-powered design, or add any required RC/filter/protection network.
  • Revisit the power tree because prior rails were designed around a higher-voltage PD input; 5 V-only input changes buck duty cycle, current, thermal, and cable current assumptions.
  • Add/validate the required 25 MHz crystal, 12.1 kΩ REXT, and remaining ASM2464PDX support circuits.

  • Executive Summary

  • What the New Datasheet Confirmed

  • What the Reference Schematic Adds

  • Current Schematic Findings

  • Good / confirmed

  • Needs change / incomplete

  • Prioritized Next Actions

  • Bottom Line

  • 2026-07-08 Update: Option A Selected

USB4 NVMe SSD Enclosure

USB4 NVMe SSD Enclosure thumbnail
USB4 external NVMe SSD enclosure PCB targeting an ASM2464PDX-class USB4 40 Gbps device controller with PCIe Gen4 x4 downstream M.2 NVMe interface, USB-C upstream port, power management, ESD protection, and controlled-impedance layout constraints.

Properties

Consumer Electronics

USB4 40 Gbps NVMe enclosure with USB-C PD input, protected VBUS, 3.3 V SSD rail, 1.05 V/1.9 V controller rails, and controlled-impedance layout requirements.

USB

USB

5

V

Bluetooth

Pricing & Availability

Distributor

Qty 1

Arrow

$12.14–$15.67

Digi-Key

$1.04

HQonline

$0.14–$0.35

LCSC

$21.87–$22.11

Mouser

$25.24–$25.32

TME

$1.08

Verical

$6.16–$7.33

Controls