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ASM2464PDX Interface Wiring Update
Decisions
- PCIe topology: intended as a single downstream PCIe Gen4 x4 port for one M.2 NVMe SSD.
- ASM
PTXsignals are host/controller transmitters and should go to the SSD receiver-side M.2 pins. - ASM
PRXsignals are controller receivers and should come from the SSD transmitter-side M.2 pins. - ASM Type-C CC pins were not tied in parallel with STUSB4500 CC pins because that would create two active CC/PD controllers on the same CC lines.
- ASM
VBUSwas not tied directly to raw VBUS because the design negotiates ~9 V and the ASM2464PDX VBUS input is 5 V tolerant per the PDF excerpt.
Wired in this pass
SPI flash
U1:SPI_CS#→ASM_SPI_CS_N_UNEXPOSED→U8:/CSU1:SPI_DO→ASM_SPI_DO_IO1_UNEXPOSED→U8:DOIO1U1:SPI_DI→ASM_SPI_DI_IO0_UNEXPOSED→U8:DIIO0U1:SPI_CLK→ASM_SPI_CLK_UNEXPOSED→U8:CLK
WP and HOLD/RESET remain on their existing pull-up placeholder nets and still need final strap validation.Reset / power control
U1:RST#→ASM2464PD_RST_N_UNEXPOSED→U9:~RESETU1:HDDPC→SSD_PWR_EN_FROM_ASM2464PD_HDDPC_UNEXPOSED→U7:ON
M.2 sideband and refclk
U1:REFCLKP0→M2_REFCLKP_FROM_ASM2464PD_UNEXPOSED→J2:55U1:REFCLKN0→M2_REFCLKN_FROM_ASM2464PD_UNEXPOSED→J2:53U1:PERST0#→M2_PERST_FROM_ASM2464PD_UNEXPOSED→J2:50U1:GPIO8→M2_CLKREQ_TO_ASM2464PD_UNEXPOSED→J2:52U1:GPIO22→M2_PEWAKE_TO_ASM2464PD_UNEXPOSED→J2:54
Type-C sideband / policy placeholders
U1:SBU1→USB_C_SBU1U1:SBU2→USB_C_SBU2U1:CC1→ASM_CC1_POLICY_PENDING_DNP(not connected to connector CC yet)U1:CC2→ASM_CC2_POLICY_PENDING_DNP(not connected to connector CC yet)U1:VBUS→ASM_VBUS_SENSE_PENDING_DIVIDER(requires divider/protection before raw VBUS)U1:REXT→ASM_REXT_12K1_REQUIRED(needs external 12.1 kΩ ±1% resistor)
PCIe lanes
Wired lanes 0–2 to the current J2 symbol using conservative M.2 mapping:
- Lane 0:
PTXP0/PTXN0↔J2:43/41;PRXP0/PRXN0↔J2:49/47 - Lane 1:
PTXP1/PTXN1↔J2:31/29;PRXP1/PRXN1↔J2:37/35 - Lane 2:
PTXP2/PTXN2↔J2:19/17;PRXP2/PRXN2↔J2:25/23
Lane 3 was not left connected because the current J2 symbol already treats candidate pins
5 and 11 as GND. I disconnected U1:PTXP3, U1:PTXN3, U1:PRXP3, and U1:PRXN3 and left them as explicit pending/no-connect until the connector symbol pin functions are verified.Grouped power/ground limitation
The current ASM2464PDX Flux component still uses grouped terminals for repeated power/ground/NC balls:
VDD_GROUPVCCL_GROUPVCCH_GROUPGND_GROUPGNDA_GROUPNC_GROUP
This is not production-ready for HDI fanout/routing. Expanding these requires editing/recreating the ASM2464PDX component itself with individual ball terminals for all 273 balls, then replacing U1 again. The current project wiring records schematic intent but should not be treated as final layout data for the BGA power/ground escape.
Required follow-up
- Verify the M.2 connector symbol pin functions against the 91302-67-067R2M datasheet before wiring lane 3.
- Add the
REXT12.1 kΩ resistor network. - Decide Type-C policy architecture: ASM-owned CC or STUSB4500-owned PD power-only with ASMedia-approved interface. Do not populate both CC paths directly.
- Add a 5 V-safe ASM VBUS sense/protection network if required by the ASMedia reference design.
- Expand ASM2464PDX grouped power/ground/NC pins into individual balls before final routing.
Decisions
Wired in this pass
SPI flash
Reset / power control
M.2 sideband and refclk
Type-C sideband / policy placeholders
PCIe lanes
Grouped power/ground limitation
Required follow-up
