The independent review caught several unsafe issues in the first implementation, so I’m correcting them before closing: overvoltage on U3 EN/UVLO, TPS65987D dead-battery boot strapping, unsuitable TVS selection, and the connector’s 20 Gbps limitation.
Work is paused because no ACUs are currently available, so I could not retrieve or verify the executor’s final correction report.
Completed before the pause: J4 connectivity, a TPS65987D-based PD block, protected ASM VBUS sensing, a 100 × 80 mm board resize, and an independent safety review. Still requiring confirmation are the corrected U3 EN/UVLO network, TPS65987D dead-battery boot, PD-rated TVS, true 40 Gbps J4 replacement, ≥4 A SSD switch, duplicate U10 removal, and M.2 keepout.
The uploaded document is for ASM2464PD, not ASM2464PDX. It is directly useful if the project targets ASM2464PD. It can inform the architecture for ASM2464PDX, but the PDX variant still needs its own official datasheet before a final PDX schematic should be made.
Device Summary
ASM2464PD is a USB4/Thunderbolt-to-PCIe/NVMe accessory controller for external storage devices.
Key features extracted:
USB4/Thunderbolt to PCIe NVMe SSD bridge
USB4/Thunderbolt Gen3 ×2, 20 Gbps ×2 class
Legacy USB 3.2 and USB 2.0 backward compatibility
Thunderbolt 3 compatibility
PCIe Gen4 ×4 downstream port
NVMe SSD support
Integrated USB Type-C UFP CC logic
Integrated BMC PHY for PD fixed 5 V UFP/Sink mode
External SPI ROM support for customized RAM code
I2C, GPIO, and UART support
Local 25 MHz crystal
PCIe 100 MHz differential reference clock output
Package
Package: 10 mm × 10 mm FC-CSP
Ball pitch: 0.460 mm
Ball count: 273
Nominal ball diameter: 0.230 mm
Maximum total thickness: 0.982 mm
Recommended outer-row footprint pad: 7 mil × 13 mil oblong pads
Power Rails
Table
Rail
Typical Voltage
Range
Function
VCCH
3.3 V
3.0–3.6 V
High-voltage I/O / Type-C / GPIO domain
VCCA33
3.3 V
likely same 3.3 V domain
Analog high-voltage supply
VCCL
1.9 V
1.85–1.95 V
Low-voltage PHY supply
VDD
1.05 V
1.0–1.1 V
Core supply
VBUS
5 V tolerant input
—
USB VBUS sense/input
Maximum current consumption listed:
Table
Rail
Max Current
VCCH
9.45 mA
VCCL
455.7 mA
VDD
1812.3 mA
This means the 1.05 V rail is high-current and must be designed carefully for DC drop, transient response, and thermal dissipation.
Power-On Sequence
Extracted sequencing requirements:
Table
Parameter
Requirement
VCCH after 5 V/VBUS present
3–6 ms after 5 V/VBUS reaches 90%
VCCL after VCCH
0–10 ms, typical 5 ms
VDD after VCCH
max 90 ms
RST# ready after VCCH
max 0 ms listed
25 MHz clock after RST# assertion
max 10 ms
PCIe REFCLK after RST# assertion
max 100 ms
PCIe PERST# after REFCLK
max 100 µs
USB-C / USB4 Pins
Table
Function
Pins
USB2 D+ / D−
UDP M1, UDM M2
USB4/SS TX lane 0
UTXP0 T1, UTXN0 T2
USB4/SS TX lane 1
UTXP1 V2, UTXN1 V1
USB4/SS RX lane 0
URXP0 P1, URXN0 P2
USB4/SS RX lane 1
URXP1 Y2, URXN1 Y1
CC
CC1 AA6, CC2 Y6
SBU
SBU1 K1, SBU2 J1
VBUS sense/input
VBUS G1
Datasheet warning: for USB SuperSpeed/USB4 pins, do not use multi-line/port TVS/ESD packages to minimize crosstalk.
PCIe / NVMe Pins
Table
Function
Pins
PCIe REFCLK output
REFCLKP0 AA8, REFCLKN0 Y8
PCIe RX lane 0
PRXP0 N21, PRXN0 N20
PCIe RX lane 1
PRXP1 W21, PRXN1 W20
PCIe RX lane 2
PRXP2 Y19, PRXN2 AA19
PCIe RX lane 3
PRXP3 AA13, PRXN3 Y13
PCIe TX lane 0
PTXP0 R20, PTXN0 R21? OCR did not clearly list PTXN0 pin; verify from ball map before schematic
GPIO0–GPIO27 subset listed; many internal weak pull-high
UART
UART_RX A21, UART_TX B21
Reset
RST# H1
Test
TEST_EN H21, internal weak pulldown
External resistor
REXT AA3 requires 12.1 kΩ ±1%
Strapping
Table
Strap Pin
Function
High
Low
GPIO5 / SPI_DO
SKT_DET / PCIe hot-plug support
Support
No support
UART_TX
MEMREPAIR
Enable
Disable
Thermal Notes
The datasheet recommends a system-level thermal solution such as a heatsink, silicone thermal interface pad, or metal housing. Thermal data is shown with a 15 mm × 15 mm × 15 mm heatsink at 35 °C ambient.
Schematic Implications
A credible ASM2464PD enclosure schematic needs:
ASM2464PD custom part/symbol/footprint from the 273-ball FC-CSP pinout
USB-C receptacle wired to USB4, USB2, CC, SBU, VBUS sense
M.2 M-key connector wired for PCIe Gen4 ×4, REFCLK, PERST#, CLKREQ#, 3.3 V, ground, and module presence pins as required
25 MHz crystal network
SPI flash footprint
12.1 kΩ ±1% REXT
Reset generation and power sequencing
Regulators for 3.3 V, 1.9 V, and high-current 1.05 V
SSD 3.3 V power switch controlled by HDDPC or reference-design equivalent
Thermal design tied into enclosure metalwork
Can schematic capture proceed?
Yes, if the design target is changed from ASM2464PDX to ASM2464PD and the user accepts that this is a 40 Gbps USB4/TB3-compatible NVMe bridge target based on the uploaded datasheet.
No, for ASM2464PDX specifically, unless an ASM2464PDX datasheet/pinout is provided.