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ASM2464PD Custom Component Source
Status
Prepared as the source-of-truth for creating a full custom Flux component. A simplified KiCad symbol has now been imported as a schematic placeholder, but the full production component is not complete because the imported symbol only exposes a small subset of the 273 balls.
Imported placeholder component:
  • ASM2464PD: /jonathanmckinney/asm2464pd
  • Source: user-uploaded ASM2464PD.kicad_sym
  • Pin coverage: 14-pin simplified symbol, not full 273-ball symbol
  • Footprint property in symbol: Package_BGA:FC-CSP-273_10.0x10.0mm_Pitch0.46mm
Altium demo-board import attempt:
  • Source archive: ASM2464PD DEMO Board B2 [Altium Designer].zip.
  • Import produced a second ASM2464PD component project: /jonathanmckinney/asm2464pd
  • Test insertion as U10 exposed no schematic pins, so it cannot replace the current 14-pin U1 placeholder.
  • U10 was removed from the enclosure project after inspection.
  • The archive may still contain useful PCB footprint data, but the importer did not recover a usable full 273-pin symbol/part in this session.
Altium source-file follow-up:
  • Uploaded ASM2464PD.SchDoc confirms the main ASM2464PD component exists in the schematic as LibReference=TEST_CHIP_BGA273_1, SourceLibraryName=ASM2464PD.SchLib, DesignItemId=TEST_CHIP_BGA273_1, and AllPinCount=273.
  • The SchDoc also references PCB model BGA273C46P21X21_1000X1000X98 with description BGA, 273-Leads, Body 10.00x10.00mmx0.98mm, Pitch 0.46mm.
  • The uploaded ASM2464PD.PrjPcb references the needed library files explicitly: ASM2464PD.SchLib and ASM2464PD.PcbLib.
  • Those library files were not included in the latest upload, so the cleanest path is still to upload ASM2464PD.SchLib and ASM2464PD.PcbLib directly.
Workflow decision:
  • Use the imported ASM2464PD placeholder for early schematic block wiring where exposed pins are sufficient.
  • Before final ERC/layout, expand or replace the placeholder with the full 273-ball component based on this source file and the original ASM2464PD PDF.
  • When transitioning to physical layout, attach a custom 0.460 mm pitch FC-CSP footprint and HDI/via-in-pad rules.
Component Identity
  • Manufacturer: ASMedia
  • MPN: ASM2464PD
  • Description: USB4/Thunderbolt to PCIe Gen4 x4 NVMe bridge/accessory controller for external SSD enclosures.
  • Package: 10 mm × 10 mm FC-CSP, 273 balls, 0.460 mm pitch
  • Designator prefix: U
  • Datasheet source: User-uploaded ASM2464PD.pdf
Electrical Summary
  • USB4/Thunderbolt Gen3 x2 upstream interface
  • PCIe Gen4 x4 downstream interface
  • USB2/USB3.2 backward compatibility
  • Integrated Type-C CC logic with internal 5.1 kΩ Rd on CC1/CC2
  • Integrated BMC PHY for PD fixed 5 V sink mode
  • External SPI ROM support
  • 25 MHz local crystal
  • 100 MHz PCIe reference clock output
Power Pins / Rails

Table

RailVoltagePins / Notes
VCCH3.3 VD13, E13, F13, D9, E9, D8, E8, D6, E6, F6, H6
VCCA333.3 VH5
VCCL1.9 VL21, L20, L18, L17, L16, N16, P16, T16, U16, U14, U13, U11, U6, T6, P6, N6, L6
VDD1.05 VJ21, J20, K21, K20, J18, J17, J16, H16, F16, E16, D16, J14, J13, H14, H13, F14, E14, D14, L11, L14, N14, P14, T14, P13, T13, E11, F11, H11, T11, F9, H9, J9, J8, L8, N8, P8, T9, T8, U9, U8
VBUS5 V tolerant inputG1
GNDDigital groundK2, D4, E4, F4, H4, J4, D5, E5, F5, J5, J6, F8, H8, L9, N9, P9, D11, J11, N11, P11, L13, N13, D17, E17, F17, H17, D18, E18, F18, H18
GNDAAnalog groundM21, M20, P21, P20, T21, T20, V21, V20, Y21, Y20, AA21, AA20, Y18, Y16, Y14, Y12, Y9, Y5, Y3, AA18, AA16, AA14, AA12, AA9, AA5, N18, N17, P18, P17, T18, T17, U18, U17, V18, V17, V16, V14, V13, V11, V9, V8, V6, L5, L4, N5, N4, P5, P4, T5, T4, U5, U4, V5, V4, AA1, AA2, W1, W2, U1, U2, R1, R2, N1, N2, L1, L2
High-Speed USB-C / USB4 Pins

Table

Pin NameBallTypeNotes
UDPM1USB2 IOUSB2 D+
UDMM2USB2 IOUSB2 D-
UTXP0T1Diff outUSB4/SS TX lane 0 P
UTXN0T2Diff outUSB4/SS TX lane 0 N
UTXP1V2Diff outUSB4/SS TX lane 1 P
UTXN1V1Diff outUSB4/SS TX lane 1 N
URXP0P1Diff inUSB4/SS RX lane 0 P
URXN0P2Diff inUSB4/SS RX lane 0 N
URXP1Y2Diff inUSB4/SS RX lane 1 P
URXN1Y1Diff inUSB4/SS RX lane 1 N
CC1AA6IOType-C CC1, built-in 5.1 kΩ Rd
CC2Y6IOType-C CC2, built-in 5.1 kΩ Rd
SBU1K1IOType-C SBU1
SBU2J1IOType-C SBU2
PCIe / NVMe Pins

Table

Pin NameBallTypeNotes
REFCLKP0AA8Diff outPCIe 100 MHz refclk P
REFCLKN0Y8Diff outPCIe 100 MHz refclk N
PRXP0N21Diff inPCIe lane 0 RX P
PRXN0N20Diff inPCIe lane 0 RX N
PRXP1W21Diff inPCIe lane 1 RX P
PRXN1W20Diff inPCIe lane 1 RX N
PRXP2Y19Diff inPCIe lane 2 RX P
PRXN2AA19Diff inPCIe lane 2 RX N
PRXP3AA13Diff inPCIe lane 3 RX P
PRXN3Y13Diff inPCIe lane 3 RX N
PTXP0R20Diff outPCIe lane 0 TX P
PTXN0R21Diff outPCIe lane 0 TX N — visually confirmed by user in Figure 2 ball map
PTXP1U20Diff outPCIe lane 1 TX P
PTXN1U21Diff outPCIe lane 1 TX N
PTXP2Y17Diff outPCIe lane 2 TX P
PTXN2AA17Diff outPCIe lane 2 TX N
PTXP3Y15Diff outPCIe lane 3 TX P
PTXN3AA15Diff outPCIe lane 3 TX N
PERST0#G21OutputPCIe reset
HDDPCC21OutputNVMe SSD power control
Clock / Reset / Configuration Pins

Table

Pin NameBallNotes
XIAA425 MHz crystal input
XOY425 MHz crystal output
REXTAA312.1 kΩ ±1% external resistor
RST#H1Power-on reset input
TEST_ENH21Test enable, internal weak pulldown
I2C_CLK_PE1I2C clock, weak pull-high
I2C_DATA_PF1I2C data, weak pull-high
UART_RXA21UART RX
UART_TXB21UART TX, strap for MEMREPAIR
SPI ROM Pins

Table

Pin NameBallNotes
SPI_CS#A2SPI chip select, GPIO4
SPI_DOA3SPI data out, GPIO5, strap for SKT_DET
SPI_DIA4SPI data in, GPIO7
SPI_CLKA5SPI clock, GPIO6
GPIO Pins
GPIO0 D1, GPIO1 C1, GPIO2 B1, GPIO3 A1, GPIO8 A19, GPIO14 A20, GPIO15 A6, GPIO16 A7, GPIO17 A8, GPIO18 A9, GPIO19 A10, GPIO20 A11, GPIO21 A12, GPIO22 A13, GPIO23 A14, GPIO24 A15, GPIO25 A16, GPIO26 A17, GPIO27 A18.
Straps
  • GPIO5/SPI_DO high: enable SKT_DET / PCIe hot-plug support.
  • GPIO5/SPI_DO low: no SKT_DET support.
  • UART_TX high: enable MEMREPAIR.
  • UART_TX low: disable MEMREPAIR.
No-Connect Balls
J2, H2, G2, F2, E2, D2, C2, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, C20, D20, E20, F20, G20, H20, Y7, AA7, Y10, AA10, Y11, AA11, D21, E21, F21.
Verification Needed Before Final Component
  • PTXN0 has been visually confirmed as R21 by the user from Figure 2 of the PDF.
  • Verify every power/ground ball against the original ball map before making footprint.
  • Confirm whether all NC balls should be omitted or explicitly represented as NC pins in the symbol.
Custom Component Creation Notes
The component blocker is a tooling/library availability issue, not an electrical-design unknown. ASM2464PD cannot be placed in the schematic until a Flux component exists with this verified pin/ball table and a matching FC-CSP footprint.
Update: the schematic-placement blocker is partially reduced by the imported 14-pin placeholder symbol. The layout/final-symbol blocker remains because the full 273-ball pin map and footprint are still required.
Final production component requirements:
  • Add all remaining USB4 high-speed lanes, including lane 1 TX/RX pairs.
  • Add all remaining PCIe Gen4 x4 lanes: PTX1–3 / PRX1–3 in addition to lane 0.
  • Add the 100 MHz PCIe REFCLKP/REFCLKN pair.
  • Explicitly map all VSS/GNDA and all 3.3 V / 1.9 V / 1.05 V rail balls so power delivery and decoupling are visible to ERC/layout.
  • Include SPI ROM pins, reset pins, test pins, UART/GPIO pins, and strap/configuration pins.
  • Finalize the hardware strap strategy before production schematic release, especially SPI boot/ROM behavior, socket detect behavior, MEMREPAIR strap, and test-mode disable.
Latest attachment guidance reviewed:
  • It proposes a JSON-style component initialization approach and a schematic-only placeholder strategy.
  • It only contains a small example pin subset and includes ball mappings that are not all verified against the ASM2464PD PDF.
  • Do not use that example JSON as the authoritative source. Use the pin/ball tables in this file and the original datasheet ball map.
Footprint / HDI Layout Guidance
Package assumptions:
  • Package type: FC-CSP / FCCSP.
  • Body size: approximately 10 mm × 10 mm.
  • Ball count: 273.
  • Ball pitch: 0.460 mm.
Initial custom-footprint guidance:
  • Treat this as an HDI/microvia design; standard dogbone fanout is likely impractical at 0.460 mm pitch.
  • Use NSMD BGA-style pads if compatible with the ASMedia package recommendation and fabricator rules.
  • Attachment-suggested pad diameter is about 0.25 mm, but this must be checked against the official package land pattern.
  • Assume filled/capped via-in-pad microvias are required for reliable breakout.
  • Use the project’s locked first-pass 8-layer stackup assumption.
  • Explicitly flag high-speed differential pads for via-in-pad / capped microvia treatment during layout, including at minimum PTXP0/PTXN0 at R20/R21 and USB4 TX example pads A2/A3 if those mappings are retained after datasheet verification.
  • Avoid routing stubs on USB4 and PCIe high-speed pads; use direct escape with matched microvia transitions and continuous return paths.
  • Do not finalize pad diameter, solder-mask expansion, or microvia dimensions until the ASMedia land pattern and chosen PCB fabricator HDI capabilities are confirmed.
Create the schematic symbol as logical functional blocks rather than physical rows:
  1. USB4/TBT high-speed lanes and USB2 pins
  2. PCIe Gen4 x4 lanes plus REFCLK
  3. Type-C CC/SBU and I2C/control pins
  4. SPI flash pins
  5. Crystal, reset, straps, GPIO, UART/debug
  6. Power rails: 3.3 V, 1.9 V, 1.05 V, VBUS and analog rails
  7. Ground/VSS/GNDA pins
This keeps the schematic readable while retaining exact ball mapping for layout.
Placeholder vs Production Use
The imported 14-pin placeholder is acceptable only for early schematic-block progress. It is not sufficient for:
  • Final ERC.
  • Power integrity review.
  • Differential-pair net-class completeness.
  • Layout fanout.
  • Manufacturing output.
Before layout, replace or expand the placeholder with the full 273-ball matrix component.
Most useful next source file:
  • A dedicated Altium ASM2464PD.SchLib and ASM2464PD.PcbLib pair, or an ASM2464PD.IntLib containing both. The uploaded PrjPcb confirms these are the referenced source libraries.
  • The full Altium demo-board zip and SchDoc confirm the full component exists, but Flux did not automatically recover it as a usable full-pin component without the referenced libraries.

  • Status

  • Component Identity

  • Electrical Summary

  • Power Pins / Rails

  • High-Speed USB-C / USB4 Pins

  • PCIe / NVMe Pins

  • Clock / Reset / Configuration Pins

  • SPI ROM Pins

  • GPIO Pins

  • Straps

  • No-Connect Balls

  • Verification Needed Before Final Component

  • Custom Component Creation Notes

  • Footprint / HDI Layout Guidance

  • Recommended Symbol Grouping

  • Placeholder vs Production Use

USB4 NVMe SSD Enclosure

USB4 external NVMe SSD enclosure PCB targeting an ASM2464PDX-class USB4 40 Gbps device controller with PCIe Gen4 x4 downstream M.2 NVMe interface, USB-C upstream port, power management, ESD protection, and controlled-impedance layout constraints.

Properties

Consumer Electronics

USB4 40 Gbps NVMe enclosure with USB-C PD input, protected VBUS, 3.3 V SSD rail, 1.05 V/1.9 V controller rails, and controlled-impedance layout requirements.

USB

USB

5

V

Bluetooth

Pricing & Availability

Distributor

Qty 1

Arrow

$12.14–$15.67

Digi-Key

$1.04

HQonline

$0.14–$0.35

LCSC

$21.87–$22.11

Mouser

$25.24–$25.32

TME

$1.08

Verical

$6.16–$7.33

Controls