Induction Heater Layout

flux

A 5 A fuse can be used temporarily, but 4 A is safer and preferred for this ~3 A / 72 W design.
A 5 A fuse does not limit normal current to 5 A; depending on its time-current curve, it may carry substantially more than 5 A for seconds or minutes. That reduces protection for the perfboard wiring, chokes, MOSFETs, connectors, and supply.
If using the 5 A fuse:
  • Use it only if the supply itself has a reliable 3 A current limit.
  • Ensure the fuse is rated for at least 32 VDC; an automotive blade fuse is suitable for 24 V DC.
  • Use 14–16 AWG input wiring and heavy copper buses.
  • Do not increase the supply current above 3 A merely because the fuse is 5 A.
  • Fit the fuse in the +24 V input, close to the connector.
  • Replace it with a 4 A time-delay fuse when available.
For initial tests, set the bench supply to 0.5–1 A, verify stable oscillation, and then increase gradually toward 3 A. If your power supply cannot current-limit, I would not recommend powering this build with the 5 A fuse alone.
J

jmwilson2019

E102 20Kv is this ceramic cap to large to substitute C3???

flux

No. 102 means 1,000 pF = 1 nF = 0.001 µF. C3 requires 100 nF = 0.1 µF, normally marked 104.
Therefore, the E102 is 100× too small in capacitance. Its 20 kV rating is harmless electrically but unnecessary, and the part may be physically large with long leads—poor for high-frequency bypassing.
For C3, look for:
  • Marking: 104
  • Capacitance: 100 nF / 0.1 µF
  • Voltage: 50 V minimum; 100 V preferred
  • Type: ceramic disc or small film
  • Mount with the leads as short as possible
The required part may say 104, 104K, 104Z, 0.1uF, or 100nF.
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Files

Schematic

Layout

3D View

MOSFET Heatsink Alignment
Final geometry
  • Board remains 91.44 mm × 121.92 mm; no resize was required.
  • Q1: (-17.78, -45.72) mm, Top, 0°.
  • Q2: (12.70, -45.72) mm, Top, 0°.
  • MOSFET center spacing: 30.48 mm.
  • Both devices use the same IRFP4668 model transform: local model offset (5.5, 0, 0) mm, model rotation 90° about X, identical board rotation and identical Y/Z placement.
  • Their tab mounting faces are therefore on the same physical plane. Orthographic front and oblique 3D inspections show both silver mounting faces and hole axes aligned for one straight heatsink.
Heatsink and service clearance
  • Approximate TO-247 body-edge gap between Q1 and Q2: 14.11 mm.
  • Approximate body clearance to the bottom board edge: 12.70 mm.
  • The strip between the TO-247 bodies and the bottom edge contains no components, preserving heatsink, insulating-pad, shoulder-washer, screw/nut and tool access.
  • Both mounting holes are fully visible from the common tab-face side.
  • Electrically isolating pads and shoulder washers remain mandatory because both tabs are drains on different resonant nodes.
J4 corridor
  • J4 remains at (3.81, -27.94) mm, 0°, with its wire-entry direction facing downward.
  • Its body fits in the central corridor between the two MOSFET body envelopes.
  • Vertical clearance from the J4 body to the MOSFET bodies is approximately 10.41 mm.
  • With the final 30.48 mm MOSFET spacing, J4 has approximately 2.87 mm lateral clearance to Q1's body and 1.09 mm to Q2's body.
Moved immediate cluster
To rotate the power stage into the coplanar arrangement, these neighbors were repositioned:
  • Tank capacitors: C4 (5.08, -2.54), C5 (5.08, -10.16), C6 (5.08, -17.78), all 0° and parallel.
  • Chokes: L1 (-17.78, 15.24) at 0°; L2 (33.02, -10.16) at 180°.
  • Q1 gate neighborhood: R6 (-27.94, -38.10), D3 (-35.56, -38.10), R8 (-17.78, -33.02), D5 (-17.78, -27.94).
  • Q2 gate neighborhood: R7 (2.54, -38.10), D4 (-5.08, -38.10), R9 (12.70, -33.02), D6 (12.70, -27.94).
  • Bias resistors: R4 (-40.64, -25.40), R5 (-25.40, -20.32).
  • The direct-bus and J4 warning silkscreen labels were moved to match the rotated cluster.
Input-area clearance
  • C2 remains at (-12.70, 50.80) mm.
  • F1 was shifted to (10.16, 43.18) mm to provide clear visible corner separation from C2; their projected X body gap is approximately 1.84 mm.
Verification
No traces were added. Final physical checks report no open errors or warnings for component overlap, out-of-bounds placement, pad access, edge placement, keepouts, invalid pads or overlapping copper. Placement-stage airwires remain intentionally unresolved.

  • Final geometry

  • Heatsink and service clearance

  • J4 corridor

  • Moved immediate cluster

  • Input-area clearance

  • Verification