# Unnecessary Lime Warp Drive ## Description ALU educativa 8-bit (ADD/SUB/INC/DEC) con display 7 segmentos (catodo comun) ## Project Details - **Owner:** jluivc - **Created:** 3/13/2026 - **Last Updated:** 3/13/2026 - **Visibility:** Public - **System Architecture:** flowchart TD A_inputs["Inputs A[7:0], B[7:0], OP[1:0]"] --> Core Core["ALU Core 8-bit adder with operand conditioning"] --> Res Res["RESULT[7:0]"] --> Nib Nib["Lower nibble RESULT[3:0]"] --> Dec Dec["HEX to 7-seg decoder combinational logic"] --> Seg Seg["7-seg display common cathode + 7 resistors"] Pwr["Power VCC, GND"] --> Core Pwr --> Dec Pwr --> Seg *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/jluivc/unnecessary-lime-warp-drive](https://www.flux.ai/jluivc/unnecessary-lime-warp-drive).* --- *Generated from [https://www.flux.ai/jluivc/unnecessary-lime-warp-drive](https://www.flux.ai/jluivc/unnecessary-lime-warp-drive)*