Schematic Batch Handoff
Status
Electrical construction completed: 33 components, 26 nets, four functional groups. This is not completion of the overall design and is not manufacturing-ready.
Completed: USB/bridge reference block, two-transistor auto-program block, target header, manual buttons, optional EN capacitor link, power/TX/RX LEDs, monitor testpoints, passive MPN/value/package metadata, logical net inspection, DC truth-table simulation, ERC readback.
Failed/blocked: finished readable schematic drafting. Available editing scope did not expose symbol-arrangement or visual-wire geometry operations; present symbols are widely spread and predominantly label-connected. The lead must finish and visually review drafting.
Unattempted: intentional PCB outline, placement, stackup and routing (approval checkpoint preserved); target physical pin mapping; bench testing; final exact CP2102N configuration procedure; specification update and full Board Bring-Up Plan.
Electrical construction
U1 CP2102N-A02-GQFN24 is USB-bus powered; local 3V3 feeds VDD/VIO. USB VBUS divider uses R3=22.1k and R4=47.5k. R1/R2 are independent 5.1k CC pulldowns. C1/C2=4.7uF, C3/C4=100nF. R5=1k bridge reset pullup. These are implemented schematic values, not a statement of independently completed capacitor-bias qualification.
J1 was rebuilt as UJ20-C-H-G-MSMT-1-P16-TR because the original connector library shield stakes did not expose logical terminals. D+/D- duplicate contacts are joined; four shield terminals are grounded. A final connector pin-to-pad geometry audit remains necessary before PCB approval.
Q1 collector=TARGET_EN, emitter=UART_RTS, base via R6=10k from UART_DTR. Q2 collector=TARGET_BOOT, emitter=UART_DTR, base via R7=10k from UART_RTS. No target pullup is tied to the adapter supply. C5=1uF is connected only through JP1; JP1 defaults open.
J2 pins 1–5: adapter TX to target RX, adapter RX from target TX, GND, BOOT/GPIO0, EN. No target power pin. R8/R9=470 ohms limit UART fault current but do not guarantee prevention of unpowered-device injection. Manual BOOT/RESET ground only the corresponding control net.
Activity LED wiring uses native GPIO0/TXT and GPIO1/RXT, not UART loading. Provisioning is mandatory; do not promise activity with factory GPIO defaults. Exact configurator fields remain unresolved.
TP1=GND, TP2=local3V3 (not target power), TP3=current-limited USB5V monitor through R13=1k. TP3 is high-impedance measurement output only: no external injection.
Verification evidence
Read-only selected ERC/DRC review at 2026-10-07T19:06:56.979Z returned two undriven-net Errors at J1 VBUS terminals and 68 PCB airwire Errors. VBUS is externally supplied by the USB host; the two ERC errors require explicit disposition, not a claim of clean ERC. Airwires are expected for the intentionally unrouted PCB, but still block manufacturing. No selected floating-pin, driver-conflict, shorted-component, single-pin, no-connect, missing-footprint or MPN issue was returned. Legibility requests returned no itemized result and are not evidence of a finished drawing.
Nominal DC simulation used the onsemi Qmmbt3904lt1g model at 27C and external fixture-only 3.3V/10k pullups. Physical RTS/DTR HH, HL, LH, LL produced EN/BOOT HH, HL, LH, HH respectively; released=3.300V, low=0.037961V. Maximum reverse VBE=3.3V. Conducting collector current=326.204uA; base current=262.854uA. These results do not establish target timing, power-off behavior or real host drive performance. Fixture pullups were not added to the schematic.
Remaining gates and safety
Only an independently powered, confirmed 3.3V logic target may connect. This adapter is not galvanically isolated. Never connect to a mains-referenced controller or a controller whose isolation is uncertain. Verify isolation and ground compatibility before attaching a USB host. Do not infer the Levoit physical pinout from this schematic.
Before target use: inspect soldering/shorts, verify local rails without target, enumerate USB in both orientations, verify UART loopback, provision and read back GPIO activity modes using CP2102N-specific instructions, exercise physical RTS/DTR states against external pullup fixture, test manual controls and default-open capacitor link, then confirm target mapping and safe power sequencing. Android USB-host enumeration does not guarantee that an app exposes DTR/RTS or supports flashing; bench-test the intended app.
Other open facts: effective MLCC capacitance/DC bias, button resting-contact verification, new J1 footprint bounds/pad mapping, exact target reset RC, supported baud/cable loading, hand-solder practicality of QFN exposed pad, full power/inrush budget, normalization of custom package-code metadata, independent risk review. Do not treat the annotated 50mA/30mA net budgets as measured limits.