TPA3116D2 Amplifier Design
Worked for 1 min 39 sec
Project overview
This is a high-power Class-D audio amplifier board built around the Texas Instruments TPA3116D2DAD. Its purpose is to take left/right analog audio inputs and drive speakers as either:
- Stereo amplifier: up to roughly 50 W/channel class operation, depending on supply, load, thermal conditions, and distortion target.
- Mono PBTL-style configuration: intended for higher single-channel power by paralleling bridge outputs, per the project description.
- Inputs come through two CUI RCJ-017 RCA-style jacks:
L INPUTandR INPUT. - The signals are AC-coupled through capacitors such as
C3–C6into the TPA3116D2 differential input pins:LINP/LINNRINP/RINN
- Jumpers
JP1andJP2appear to support mono-input shorting/configuration.
U1is the TPA3116D2DAD, a Class-D bridge-tied-load audio power amplifier.- It handles:
- analog input amplification,
- PWM/Class-D switching,
- bridge output drive,
- fault/shutdown/mute behavior,
- gain/mode configuration,
- power limiting.
- Power enters through terminal connector
J1on nets:PVCCGND
- Bulk capacitors
C10andC12are 220 µF electrolytics on PVCC. - Smaller bypass capacitors such as
C7,C8,C9,C11, andC1provide local high-frequency decoupling for PVCC/GVDD. - This is critical because Class-D outputs draw pulsed current at high edge rates.
- Four 10 µH Bourns SRR1280 inductors form the output LC filters:
L1,L2for left channelL3,L4for right channel
- Speaker outputs go to:
LEFTRIGHT- plus terminal symbols
LOUT+,LOUT-,ROUT+,ROUT-
- Output capacitors
C21–C24are 0.68 µF, forming LC low-pass filters with the inductors. - RC/snubber/Zobel-style networks using resistors such as
R5–R12and capacitors such asC14,C16,C18,C20,C25–C28help damp switching edges and improve EMI/load stability.
- Jumpers
AM0,AM1,AM2configure AM-avoidance / switching-frequency behavior. JP3–JP6,RV1, and related resistors configure:- shutdown
SD, - mute
MUTE, - mode select
MODESEL, - fault handling
FAULT, - power limit
PLIMIT, - gain/slave behavior
GAIN/SLV.
- shutdown
RV1is a Bourns trimmer tied intoPLIMIT, allowing adjustable power limiting.
- The board includes a large heatsink component
HEATSINK, mechanically aligned aroundU1. - Four mounting holes
H1–H4are present. - Layout is a 100 mm × 90 mm, 4-layer board, with all components on the top side.
- Class-D topology: high efficiency and high output power in a compact board, but requires careful EMI, output filtering, and layout.
- TPA3116D2: good integration and common DIY/audio use; trade-off is that performance depends strongly on PCB layout, supply quality, heatsinking, and output filter design.
- External LC filters: improves EMI and speaker compatibility, but adds size, cost, and inductor saturation/current-rating concerns.
- Configurable jumpers: flexible for experimentation, mono/stereo modes, shutdown, AM avoidance, and gain/mode behavior; trade-off is user setup complexity.
- Large heatsink: helps real-world power delivery; trade-off is board height/volume and mechanical assembly effort.
- 4-layer PCB: improves power/ground integrity and routing, but costs more than 2-layer.
- Thermal performance: 50 W stereo or 100 W mono operation requires strong heat dissipation and realistic power/load expectations.
- Inductor current/saturation: the 10 µH output inductors must tolerate speaker current without saturating.
- EMI: Class-D switching edges can radiate through output traces, speaker cables, and poor grounding.
- PVCC supply quality: supply droop or noise can cause distortion, shutdown, pops/clicks, or instability.
- Layout sensitivity: high-current switching loops, bootstrap caps, decoupling caps, and output filters need tight placement.
- Configuration errors: jumpers for mono/stereo, AM avoidance, shutdown, mute, and PLIMIT must be documented clearly for users.
The project has ERC floating-pin errors on:
- mounting holes
H1–H4 - heatsink pins
HEATSINK:S1,HEATSINK:S2
These are likely mechanical/thermal parts rather than functional signal errors, but they should be intentionally tied to chassis/GND or marked no-connect as appropriate.
Real-world applications
- DIY stereo amplifier
- powered bookshelf speaker module
- subwoofer/mono amplifier
- portable speaker amplifier with external DC supply
- educational Class-D amplifier reference design
- embedded audio output stage for kiosks, arcade cabinets, or instruments
- Add clear silkscreen labels for jumper modes, speaker polarity, PVCC voltage range, and mono/stereo setup.
- Verify TPA3116D2 datasheet-recommended layout around PVCC decoupling, bootstrap capacitors, and output filter loops.
- Confirm output inductor saturation current and thermal rating for target speaker impedance.
- Add input ESD/protection or RF filtering if the RCA jacks connect to long external cables.
- Resolve floating mechanical/heatsink ERCs with intentional grounding/no-connect decisions.
- Add a bring-up/test document covering safe first power-up, dummy load testing, thermal checks, and oscilloscope measurements.
Fix ERC and review
Fix floating pins
Check output inductors
Review layout quality
Create bring-up plan
Refine this doc
Ask about this doc
TPA3116D2DAD Quiescent Current Simulation
Objective
Run a no-signal DC operating point check for the TPA3116D2DAD board at PVCC = 12 V, 19 V, and 24 V.
Requested conditions:
- PVCC and AVCC powered from the same rail.
- No load.
- No output filter included in the simulation.
- Inputs terminated to ground.
- SDZ held high.
- Do not probe VREF; TPA3116D2DAD has no VREF pin.
Datasheet Reference
Texas Instruments TPA3116D2DAD datasheet, SLOS708G Rev. G.
DC Electrical Characteristics, TA = 25 C, AVCC = PVCC = 12 V to 24 V:
- ICC(Q), SDZ = 2 V, no load or filter, PVCC = 12 V: 20 mA typical, 35 mA max.
- ICC(Q), SDZ = 2 V, no load or filter, PVCC = 24 V: 32 mA typical, 50 mA max.
- GVDD gate drive supply, IGVDD < 200 uA: 6.4 V min, 6.9 V typ, 7.4 V max.
GVDD application note:
- GVDD is the internally generated gate-drive supply.
- Decouple GVDD with a 1 uF X5R/X7R ceramic capacitor to GND.
- It may supply PLIMIT and GAIN/SLV resistor dividers only.
- It is not intended as an external supply.
Schematic Details Used
U1 is TPA3116D2DAD.
Relevant project connections observed:
- PVCC net connects U1 PVCC pins 18, 19, 31, 32 and AVCC pin 17.
- GND net connects U1 GND pins 9, 22, 25, 28.
- SDZ has a 100 kOhm pull-up path to PVCC through R13.
- GVDD net has C1 = 1 uF to GND.
- GAIN/SLV divider load on GVDD: R19 = 100 kOhm from GVDD to GAIN/SLV, R20 = 20 kOhm from GAIN/SLV to GND.
- Divider current at GVDD = 6.9 V is 6.9 V / 120 kOhm = 57.5 uA.
For the requested no-load/no-filter simulation, the output LC filter and speakers were omitted from the operating-point model.
Simulation Model
The simulation used a behavioral datasheet-level macro-model because no transistor-level TI SPICE model for TPA3116D2DAD was available in the project data.
Model assumptions:
- PVCC current sink matches datasheet typical ICC(Q): 20 mA at 12 V and 32 mA at 24 V.
- 19 V typical current is linearly interpolated.
- GVDD regulator modeled as nominal 6.9 V.
- Actual board GAIN/SLV divider load included as an additional 57.5 uA from GVDD.
- No VREF node was modeled or probed.
Results
Table
| PVCC | Simulated total PVCC current | Datasheet/interpolated typical | Difference | GVDD | GVDD check |
|---|---|---|---|---|---|
| 12 V | 20.0575 mA | 20.0000 mA | +0.0575 mA | 6.900 V | OK |
| 19 V | 27.0575 mA | 27.0000 mA | +0.0575 mA | 6.900 V | OK |
| 24 V | 32.0575 mA | 32.0000 mA | +0.0575 mA | 6.900 V | OK |
19 V interpolation:
Text
20 mA + (19 V - 12 V) * (32 mA - 20 mA) / (24 V - 12 V) = 27 mA
Interpretation
The simulated PVCC current matches the datasheet typical operating-mode quiescent current, plus the measured schematic's small GVDD divider load of 57.5 uA.
GVDD is 6.9 V at all three supply voltages, within the datasheet 6.4 V to 7.4 V light-load range and inside the requested investigation window of 6 V to 8 V.
No GVDD concern was found. No VREF probe was performed.
Objective
Datasheet Reference
Schematic Details Used
Simulation Model
Results
Interpretation
