I want to validate gain accuracy on my TPA3116D2DAD design. The chip has four selectable gain settings set by a resistor voltage divider on the GAIN/SLV pin between GVDD and GND. R19 and R20 is the voltage divider.

For this gain setting, apply a 1kHz sine wave at 100mV RMS to one channel input, single-ended, AC-coupled. Load the output with a 4Ω resistive dummy load. Power supply at 24V on PVCC.

Measure the output voltage across the load and calculate actual gain in dB. Compare against the datasheet expected values.

Two things to flag: first, if this gain setting lands outside the ±1 dB tolerance band, that points to a resistor value or GVDD voltage problem. Second, note that the gain setting is latched during power-up and cannot be changed while the device is powered, so this gain setting needs to be simulated as a separate run with the resistors configured before the supply comes up, not switched mid-simulation.

Also confirm the input bias point. The LINP, LINN, RINP, RINN input pins are internally biased at 3V, so the AC-coupled input should be sitting on a 3V DC bias at the pin. Flag if the bias point is significantly off, that would indicate the input coupling cap is loading the internal bias network incorrectly.

I’ll validate the TPA3116D2 gain setting from the actual R19/R20 divider and input/output network, then record the calculated/simulated gain and bias checks in a project file.

Validated. R19 = 100 kΩ to GVDD and R20 = 20 kΩ to GND selects the datasheet Master 26 dB gain state; simulated output is 1.99524 Vrms across 4 Ω for 100 mVrms input, giving 25.9999 dB, so it passes the ±1 dB band.

Input bias also passes: LINP ≈ 2.99546 V and LINN ≈ 2.99547 V, close to the expected 3 V internal bias. I recorded the full calculation, datasheet comparison, latch-behavior note, and bias check in TPA3116D2DAD Gain Accuracy Validation.