# XC7Z020-1CLG400I (Component) ## Description Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Zynq®-7000 Artix™-7 FPGA, 85K Logic Cells 667MHz 400-CSPBGA (17x17) #CommonPartsLibrary #IntegratedCircuit #Embedded #SoC ## Component Details - **Owner:** jecstronic - **Created:** 2/17/2024 - **Last Updated:** 2/17/2024 - **Visibility:** Public - **License:** https://creativecommons.org/licenses/by/4.0/ - **Part Type:** Integrated Circuit - **Manufacturer Name:** AMD - **Manufacturer Part Number:** XC7Z020-1CLG400I - **Datasheet URL:** https://www.mouser.com/datasheet/2/903/ds190_Zynq_7000_Overview-1595492.pdf - **Used in:** 12 projects ## Distributor Pricing (qty 1) *Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.* | Distributor | Unit Price (qty 1) | Stock | |------------|--------------------|-------| | [Digi-Key](https://www.digikey.com/en/products/detail/amd/XC7Z020-1CLG400I/3925188) | $157.30 | 45 | | [LCSC](https://www.lcsc.com/product-detail/C1519081.html) | $30.7199 | 89 | | [Mouser](https://www.mouser.com/ProductDetail/AMD-Xilinx/XC7Z020-1CLG400I?qs=rrS6PyfT74dBkXk5SYUQpA%3D%3D) | $164.02 | 0 | - **Part Type:** Integrated Circuits - **Sub-Type:** Logic - **Manufacturer:** AMD - **MPN:** XC7Z020-1CLG400I - **Package / Case Code:** CSPBGA - **Pin Count:** 400 - **Logic Function:** AND ## Pins | Pin | Name | Type | |-----|------|------| | A1 | PS_DDR_DM0_502 | | | A2 | PS_DDR_DQ2_502 | | | A3 | VCCO_DDR_502_1 | | | A4 | PS_DDR_DQ3_502 | | | A5 | PS_MIO6_500 | | | A6 | PS_MIO5_500 | | | A7 | PS_MIO1_500 | | | A8 | GND_1 | | | A9 | PS_MIO43_501 | | | A10 | PS_MIO37_501 | | | A11 | PS_MIO36_501 | | | A12 | PS_MIO34_501 | | | A13 | VCCO_MIO1_501_1 | | | A14 | PS_MIO32_501 | | | A15 | PS_MIO26_501 | | | A16 | PS_MIO24_501 | | | A17 | PS_MIO20_501 | | | A18 | GND_2 | | | A19 | PS_MIO16_501 | | | A20 | IO_L2N_T0_AD8N_35 | | | B1 | GND_3 | | | B2 | PS_DDR_DQS_N0_502 | | | B3 | PS_DDR_DQ1_502 | | | B4 | PS_DDR_DRST_B_502 | | | B5 | PS_MIO9_500 | | | B6 | VCCO_MIO0_500_1 | | | B7 | PS_MIO4_500 | | | B8 | PS_MIO2_500 | | | B9 | PS_MIO51_501 | | | B10 | PS_SRST_B_501 | | | B11 | GND_4 | | | B12 | PS_MIO48_501 | | | B13 | PS_MIO50_501 | | | B14 | PS_MIO47_501 | | | B15 | PS_MIO45_501 | | | B16 | VCCO_MIO1_501_2 | | | B17 | PS_MIO22_501 | | | B18 | PS_MIO18_501 | | | B19 | IO_L2P_T0_AD8P_35 | | | B20 | IO_L1N_T0_AD0N_35 | | | C1 | PS_DDR_DQ6_502 | | | C2 | PS_DDR_DQS_P0_502 | | | C3 | PS_DDR_DQ0_502 | | | C4 | GND_5 | | | C5 | PS_MIO14_500 | | | C6 | PS_MIO11_500 | | | C7 | PS_POR_B_500 | | | C8 | PS_MIO15_500 | | | C9 | GND_6 | | | C10 | PS_MIO52_501 | | | C11 | PS_MIO53_501 | | | C12 | PS_MIO49_501 | | | C13 | PS_MIO29_501 | | | C14 | GND_7 | | | C15 | PS_MIO30_501 | | | C16 | PS_MIO28_501 | | | C17 | PS_MIO41_501 | | | C18 | PS_MIO39_501 | | | C19 | VCCO_35_1 | | | C20 | IO_L1P_T0_AD0P_35 | | | D1 | PS_DDR_DQ5_502 | | | D2 | VCCO_DDR_502_2 | | | D3 | PS_DDR_DQ4_502 | | | D4 | PS_DDR_A13_502 | | | D5 | PS_MIO8_500 | | | D6 | PS_MIO3_500 | | | D7 | VCCO_MIO0_500_2 | | | D8 | PS_MIO7_500 | | | D9 | PS_MIO12_500 | | | D10 | PS_MIO19_501 | | | D11 | PS_MIO23_501 | | | D12 | VCCO_MIO1_501_3 | | | D13 | PS_MIO27_501 | | | D14 | PS_MIO40_501 | | | D15 | PS_MIO33_501 | | | D16 | PS_MIO46_501 | | | D17 | GND_8 | | | D18 | IO_L3N_T0_DQS_AD1N_35 | | | D19 | IO_L4P_T0_35 | | | D20 | IO_L4N_T0_35 | | | E1 | PS_DDR_DQ7_502 | | | E2 | PS_DDR_DQ8_502 | | | E3 | PS_DDR_DQ9_502 | | | E4 | PS_DDR_A12_502 | | | E5 | VCCO_DDR_502_3 | | | E6 | PS_MIO0_500 | | | E7 | PS_CLK_500 | | | E8 | PS_MIO13_500 | | | E9 | PS_MIO10_500 | | | E10 | GND_9 | | | E11 | PS_MIO_VREF_501 | | | E12 | PS_MIO42_501 | | | E13 | PS_MIO38_501 | | | E14 | PS_MIO17_501 | | | E15 | VCCO_MIO1_501_4 | | | E16 | PS_MIO31_501 | | | E17 | IO_L3P_T0_DQS_AD1P_35 | | | E18 | IO_L5P_T0_AD9P_35 | | | E19 | IO_L5N_T0_AD9N_35 | | | E20 | GND_10 | | | F1 | PS_DDR_DM1_502 | | | F2 | PS_DDR_DQS_N1_502 | | | F3 | GND_11 | | | F4 | PS_DDR_A14_502 | | | F5 | PS_DDR_A10_502 | | | F6 | TDO_0 | | | F7 | GND_12 | | | F8 | VCCPAUX_1 | | | F9 | TCK_0 | | | F10 | RSVDGND | | | F11 | VCCBATT_0 | | | F12 | PS_MIO35_501 | | | F13 | PS_MIO44_501 | | | F14 | PS_MIO21_501 | | | F15 | PS_MIO25_501 | | | F16 | IO_L6P_T0_35 | | | F17 | IO_L6N_T0_VREF_35 | | | F18 | VCCO_35_2 | | | F19 | IO_L15P_T2_DQS_AD12P_35 | | | F20 | IO_L15N_T2_DQS_AD12N_35 | | | G1 | VCCO_DDR_502_4 | | | G2 | PS_DDR_DQS_P1_502 | | | G3 | PS_DDR_DQ10_502 | | | G4 | PS_DDR_A11_502 | | | G5 | PS_DDR_VRN_502 | | | G6 | TDI_0 | | | G7 | VCCPINT_1 | | | G8 | VCCPLL | | | G9 | VCCPAUX_2 | | | G10 | GND_13 | | | G11 | VCCBRAM_1 | | | G12 | GND_14 | | | G13 | VCCINT_1 | | | G14 | IO_0_35 | | | G15 | IO_L19N_T3_VREF_35 | | | G16 | GND_15 | | | G17 | IO_L16P_T2_35 | | | G18 | IO_L16N_T2_35 | | | G19 | IO_L18P_T2_AD13P_35 | | | G20 | IO_L18N_T2_AD13N_35 | | | H1 | PS_DDR_DQ14_502 | | | H2 | PS_DDR_DQ13_502 | | | H3 | PS_DDR_DQ11_502 | | | H4 | VCCO_DDR_502_5 | | | H5 | PS_DDR_VRP_502 | | | H6 | PS_DDR_VREF0_502 | | | H7 | GND_16 | | | H8 | VCCPAUX_3 | | | H9 | GND_17 | | | H10 | VCCBRAM_2 | | | H11 | GND_18 | | | H12 | VCCINT_2 | | | H13 | GND_19 | | | H14 | VCCO_35_3 | | | H15 | IO_L19P_T3_35 | | | H16 | IO_L13P_T2_MRCC_35 | | | H17 | IO_L13N_T2_MRCC_35 | | | H18 | IO_L14N_T2_AD4N_SRCC_35 | | | H19 | GND_20 | | | H20 | IO_L17N_T2_AD5N_35 | | | J1 | PS_DDR_DQ15_502 | | | J2 | GND_21 | | | J3 | PS_DDR_DQ12_502 | | | J4 | PS_DDR_A9_502 | | | J5 | PS_DDR_BA2_502 | | | J6 | TMS_0 | | | J7 | VCCPINT_2 | | | J8 | GND_22 | | | J9 | VCCADC_0 | | | J10 | GNDADC_0 | | | J11 | VCCAUX_1 | | | J12 | GND_23 | | | J13 | VCCINT_3 | | | J14 | IO_L20N_T3_AD6N_35 | | | J15 | IO_25_35 | | | J16 | IO_L24N_T3_AD15N_35 | | | J17 | VCCO_35_4 | | | J18 | IO_L14P_T2_AD4P_SRCC_35 | | | J19 | IO_L10N_T1_AD11N_35 | | | J20 | IO_L17P_T2_AD5P_35 | | | K1 | PS_DDR_A8_502 | | | K2 | PS_DDR_A1_502 | | | K3 | PS_DDR_A3_502 | | | K4 | PS_DDR_A7_502 | | | K5 | GND_24 | | | K6 | VCCO_0 | | | K7 | GND_25 | | | K8 | VCCPAUX_4 | | | K9 | VP_0 | | | K10 | VREFN_0 | | | K11 | GND_26 | | | K12 | VCCINT_4 | | | K13 | GND_27 | | | K14 | IO_L20P_T3_AD6P_35 | | | K15 | GND_28 | | | K16 | IO_L24P_T3_AD15P_35 | | | K17 | IO_L12P_T1_MRCC_35 | | | K18 | IO_L12N_T1_MRCC_35 | | | K19 | IO_L10P_T1_AD11P_35 | | | K20 | VCCO_35_5 | | | L1 | PS_DDR_A5_502 | | | L2 | PS_DDR_CKP_502 | | | L3 | VCCO_DDR_502_6 | | | L4 | PS_DDR_A6_502 | | | L5 | PS_DDR_BA0_502 | | | L6 | PROGRAM_B_0 | | | L7 | VCCPINT_3 | | | L8 | GND_29 | | | L9 | VREFP_0 | | | L10 | VN_0 | | | L11 | VCCAUX_2 | | | L12 | GND_30 | | | L13 | VCCINT_5 | | | L14 | IO_L22P_T3_AD7P_35 | | | L15 | IO_L22N_T3_AD7N_35 | | | L16 | IO_L11P_T1_SRCC_35 | | | L17 | IO_L11N_T1_SRCC_35 | | | L18 | GND_31 | | | L19 | IO_L9P_T1_DQS_AD3P_35 | | | L20 | IO_L9N_T1_DQS_AD3N_35 | | | M1 | GND_32 | | | M2 | PS_DDR_CKN_502 | | | M3 | PS_DDR_A2_502 | | | M4 | PS_DDR_A4_502 | | | M5 | PS_DDR_WE_B_502 | | | M6 | CFGBVS_0 | | | M7 | GND_33 | | | M8 | VCCPAUX_5 | | | M9 | DXP_0 | | | M10 | DXN_0 | | | M11 | GND_34 | | | M12 | VCCINT_6 | | | M13 | GND_35 | | | M14 | IO_L23P_T3_35 | | | M15 | IO_L23N_T3_35 | | | M16 | VCCO_35_6 | | | M17 | IO_L8P_T1_AD10P_35 | | | M18 | IO_L8N_T1_AD10N_35 | | | M19 | IO_L7P_T1_AD2P_35 | | | M20 | IO_L7N_T1_AD2N_35 | | | N1 | PS_DDR_CS_B_502 | | | N2 | PS_DDR_A0_502 | | | N3 | PS_DDR_CKE_502 | | | N4 | GND_36 | | | N5 | PS_DDR_ODT_502 | | | N6 | RSVDVCC3 | | | N7 | VCCPINT_4 | | | N8 | GND_37 | | | N9 | VCCAUX_3 | | | N10 | GND_38 | | | N11 | VCCAUX_4 | | | N12 | GND_39 | | | N13 | VCCINT_7 | | | N14 | GND_40 | | | N15 | IO_L21P_T3_DQS_AD14P_35 | | | N16 | IO_L21N_T3_DQS_AD14N_35 | | | N17 | IO_L23P_T3_34 | | | N18 | IO_L13P_T2_MRCC_34 | | | N19 | VCCO_34_1 | | | N20 | IO_L14P_T2_SRCC_34 | | | P1 | PS_DDR_DQ16_502 | | | P2 | VCCO_DDR_502_7 | | | P3 | PS_DDR_DQ17_502 | | | P4 | PS_DDR_RAS_B_502 | | | P5 | PS_DDR_CAS_B_502 | | | P6 | PS_DDR_VREF1_502 | | | P7 | GND_41 | | | P8 | VCCPINT_5 | | | P9 | GND_42 | | | P10 | VCCAUX_5 | | | P11 | GND_43 | | | P12 | VCCINT_8 | | | P13 | GND_44 | | | P14 | IO_L6P_T0_34 | | | P15 | IO_L24P_T3_34 | | | P16 | IO_L24N_T3_34 | | | P17 | GND_45 | | | P18 | IO_L23N_T3_34 | | | P19 | IO_L13N_T2_MRCC_34 | | | P20 | IO_L14N_T2_SRCC_34 | | | R1 | PS_DDR_DQ19_502 | | | R2 | PS_DDR_DQS_P2_502 | | | R3 | PS_DDR_DQ18_502 | | | R4 | PS_DDR_BA1_502 | | | R5 | VCCO_DDR_502_8 | | | R6 | RSVDVCC2 | | | R7 | VCCPINT_6 | | | R8 | GND_46 | | | R9 | VCCAUX_6 | | | R10 | INIT_B_0 | | | R11 | DONE_0 | | | R12 | GND_47 | | | R13 | VCCINT_9 | | | R14 | IO_L6N_T0_VREF_34 | | | R15 | VCCO_34_2 | | | R16 | IO_L19P_T3_34 | | | R17 | IO_L19N_T3_VREF_34 | | | R18 | IO_L20N_T3_34 | | | R19 | IO_0_34 | | | R20 | GND_48 | | | T1 | PS_DDR_DM2_502 | | | T2 | PS_DDR_DQS_N2_502 | | | T3 | GND_49 | | | T4 | PS_DDR_DQ20_502 | | | T5 | IO_L19P_T3_13 | | | T6 | RSVDVCC1 | | | T7 | GND_50 | | | T8 | VCCO_13_1 | | | T9 | IO_L12P_T1_MRCC_13 | | | T10 | IO_L1N_T0_34 | | | T11 | IO_L1P_T0_34 | | | T12 | IO_L2P_T0_34 | | | T13 | GND_51 | | | T14 | IO_L5P_T0_34 | | | T15 | IO_L5N_T0_34 | | | T16 | IO_L9P_T1_DQS_34 | | | T17 | IO_L20P_T3_34 | | | T18 | VCCO_34_3 | | | T19 | IO_25_34 | | | T20 | IO_L15P_T2_DQS_34 | | | U1 | VCCO_DDR_502_9 | | | U2 | PS_DDR_DQ22_502 | | | U3 | PS_DDR_DQ23_502 | | | U4 | PS_DDR_DQ21_502 | | | U5 | IO_L19N_T3_VREF_13 | | | U6 | GND_52 | | | U7 | IO_L11P_T1_SRCC_13 | | | U8 | IO_L17N_T2_13 | | | U9 | IO_L17P_T2_13 | | | U10 | IO_L12N_T1_MRCC_13 | | | U11 | VCCO_13_2 | | | U12 | IO_L2N_T0_34 | | | U13 | IO_L3P_T0_DQS_PUDC_B_34 | | | U14 | IO_L11P_T1_SRCC_34 | | | U15 | IO_L11N_T1_SRCC_34 | | | U16 | GND_53 | | | U17 | IO_L9N_T1_DQS_34 | | | U18 | IO_L12P_T1_MRCC_34 | | | U19 | IO_L12N_T1_MRCC_34 | | | U20 | IO_L15N_T2_DQS_34 | | | V1 | PS_DDR_DQ24_502 | | | V2 | PS_DDR_DQ30_502 | | | V3 | PS_DDR_DQ31_502 | | | V4 | VCCO_DDR_502_10 | | | V5 | IO_L6N_T0_VREF_13 | | | V6 | IO_L22P_T3_13 | | | V7 | IO_L11N_T1_SRCC_13 | | | V8 | IO_L15P_T2_DQS_13 | | | V9 | GND_54 | | | V10 | IO_L21N_T3_DQS_13 | | | V11 | IO_L21P_T3_DQS_13 | | | V12 | IO_L4P_T0_34 | | | V13 | IO_L3N_T0_DQS_34 | | | V14 | VCCO_34_4 | | | V15 | IO_L10P_T1_34 | | | V16 | IO_L18P_T2_34 | | | V17 | IO_L21P_T3_DQS_34 | | | V18 | IO_L21N_T3_DQS_34 | | | V19 | GND_55 | | | V20 | IO_L16P_T2_34 | | | W1 | PS_DDR_DQ26_502 | | | W2 | GND_56 | | | W3 | PS_DDR_DQ29_502 | | | W4 | PS_DDR_DQS_N3_502 | | | W5 | PS_DDR_DQS_P3_502 | | | W6 | IO_L22N_T3_13 | | | W7 | VCCO_13_3 | | | W8 | IO_L15N_T2_DQS_13 | | | W9 | IO_L16N_T2_13 | | | W10 | IO_L16P_T2_13 | | | W11 | IO_L18P_T2_13 | | | W12 | GND_57 | | | W13 | IO_L4N_T0_34 | | | W14 | IO_L8P_T1_34 | | | W15 | IO_L10N_T1_34 | | | W16 | IO_L18N_T2_34 | | | W17 | VCCO_34_5 | | | W18 | IO_L22P_T3_34 | | | W19 | IO_L22N_T3_34 | | | W20 | IO_L16N_T2_34 | | | Y1 | PS_DDR_DM3_502 | | | Y2 | PS_DDR_DQ28_502 | | | Y3 | PS_DDR_DQ25_502 | | | Y4 | PS_DDR_DQ27_502 | | | Y5 | GND_58 | | | Y6 | IO_L13N_T2_MRCC_13 | | | Y7 | IO_L13P_T2_MRCC_13 | | | Y8 | IO_L14N_T2_SRCC_13 | | | Y9 | IO_L14P_T2_SRCC_13 | | | Y10 | VCCO_13_4 | | | Y11 | IO_L18N_T2_13 | | | Y12 | IO_L20P_T3_13 | | | Y13 | IO_L20N_T3_13 | | | Y14 | IO_L8N_T1_34 | | | Y15 | GND_59 | | | Y16 | IO_L7P_T1_34 | | | Y17 | IO_L7N_T1_34 | | | Y18 | IO_L17P_T2_34 | | | Y19 | IO_L17N_T2_34 | | | Y20 | VCCO_34_6 | | --- *Generated from [https://www.flux.ai/jecstronic/xc7z020-1clg400i](https://www.flux.ai/jecstronic/xc7z020-1clg400i)*