# XC7Z010-3CLG225E (Component) ## Description Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ System On Chip (SOC) IC Zynq®-7000 Artix™-7 FPGA, 28K Logic Cells 866MHz 225-CSPBGA (13x13) #CommonPartsLibrary #IntegratedCircuit ## Component Details - **Owner:** jecstronic - **Created:** 6/13/2023 - **Last Updated:** 6/13/2023 - **Visibility:** Public - **Datasheet URL:** https://docs.xilinx.com/v/u/en-US/ds187-XC7Z010-XC7Z020-Data-Sheet - **Manufacturer Name:** AMD - **Part Type:** Integrated Circuit - **Manufacturer Part Number:** XC7Z010-3CLG225E - **License:** https://creativecommons.org/licenses/by/4.0/ - **Used in:** 16 projects ## Distributor Pricing (qty 1) *Pricing shown for quantity 1. For price breaks and other quantities, open in Flux.* | Distributor | Unit Price (qty 1) | Stock | |------------|--------------------|-------| | [Digi-Key](https://www.digikey.com/en/products/detail/amd/XC7Z010-3CLG225E/3925186) | N/A | N/A | | [LCSC](https://www.lcsc.com/product-detail/C1522078.html) | $25.4189 | 3 | | [Mouser](https://www.mouser.com/ProductDetail/AMD-Xilinx/XC7Z010-3CLG225E?qs=rrS6PyfT74cdgPEnjLusDw%3D%3D) | $111.02 | 4 | - **Part Type:** Integrated Circuits - **Sub-Type:** Logic - **Manufacturer:** AMD - **MPN:** XC7Z010-3CLG225E - **Package / Case Code:** CSPBGA - **Pin Count:** 225 - **Logic Function:** AND ## Pins | Pin | Name | Type | |-----|------|------| | A1 | GND(1) | | | A2 | PS_DDR_DQ1_502 | | | A3 | PS_DDR_DQ7_502 | | | A4 | PS_DDR_DQ5_502 | | | A5 | PS_MIO1_500 | | | A6 | VCCO_MIO0_500(1) | | | A7 | PS_MIO3_500 | | | A8 | PS_MIO2_500 | | | A9 | PS_MIO5_500 | | | A10 | PS_MIO6_500 | | | A11 | GND(2) | | | A12 | PS_MIO52_501 | | | A13 | PS_MIO38_501 | | | A14 | PS_MIO35_501 | | | A15 | PS_MIO28_501 | | | B1 | PS_DDR_DM0_502 | | | B2 | PS_DDR_DQS_N0_502 | | | B3 | VCCO_DDR_502(1) | | | B4 | PS_DDR_DQ4_502 | | | B5 | PS_MIO9_500 | | | B6 | PS_MIO8_500 | | | B7 | PS_MIO12_500 | | | B8 | GND(3) | | | B9 | PS_MIO14_500 | | | B10 | PS_MIO11_500 | | | B11 | PS_SRST_B_501 | | | B12 | PS_MIO48_501 | | | B13 | VCCO_MIO1_501(1) | | | B14 | PS_MIO36_501 | | | B15 | PS_MIO30_501 | | | C1 | PS_DDR_DQ3_502 | | | C2 | PS_DDR_DQS_P0_502 | | | C3 | PS_DDR_DQ6_502 | | | C4 | PS_DDR_DQ2_502 | | | C5 | GND(4) | | | C6 | PS_MIO13_500 | | | C7 | PS_CLK_500 | | | C8 | PS_MIO4_500 | | | C9 | PS_POR_B_500 | | | C10 | VCCO_MIO1_501(2) | | | C11 | PS_MIO33_501 | | | C12 | PS_MIO31_501 | | | C13 | PS_MIO53_501 | | | C14 | PS_MIO37_501 | | | C15 | GND(5) | | | D1 | PS_DDR_DQ9_502 | | | D2 | GND(6) | | | D3 | PS_DDR_DM1_502 | | | D4 | PS_DDR_DQ0_502 | | | D5 | INIT_B_0 | | | D6 | PS_MIO10_500 | | | D7 | VCCO_MIO0_500(2) | | | D8 | PS_MIO0_500 | | | D9 | PS_MIO7_500 | | | D10 | PS_MIO15_500 | | | D11 | PS_MIO29_501 | | | D12 | GND(7) | | | D13 | PS_MIO49_501 | | | D14 | PS_MIO39_501 | | | D15 | PS_MIO34_501 | | | E1 | PS_DDR_DQ8_502 | | | E2 | PS_DDR_DQ10_502 | | | E3 | PS_DDR_DQ11_502 | | | E4 | VCCO_DDR_502(2) | | | E5 | GND(8) | | | E6 | VCCBATT_0 | | | E7 | GND(9) | | | E8 | RSVDGND | | | E9 | GND(10) | | | E10 | VCCINT(1) | | | E11 | IO_L2P_T0_AD8P_35 | | | E12 | IO_L2N_T0_AD8N_35 | | | E13 | IO_L1N_T0_AD0N_35 | | | E14 | VCCO_MIO1_501(3) | | | E15 | PS_MIO32_501 | | | F1 | VCCO_DDR_502(3) | | | F2 | PS_DDR_DQS_N1_502 | | | F3 | PS_DDR_DQ12_502 | | | F4 | PS_DDR_VREF0_502 | | | F5 | VCCPLL | | | F6 | CFGBVS_0 | | | F7 | VCCADC_0 | | | F8 | GNDADC_0 | | | F9 | VCCINT(2) | | | F10 | GND(11) | | | F11 | VCCO_35(1) | | | F12 | IO_L1P_T0_AD0P_35 | | | F13 | IO_L3P_T0_DQS_AD1P_35 | | | F14 | IO_L3N_T0_DQS_AD1N_35 | | | F15 | IO_L5N_T0_AD9N_35 | | | G1 | PS_DDR_DQ13_502 | | | G2 | PS_DDR_DQS_P1_502 | | | G3 | GND(12) | | | G4 | RSVDVCC1 | | | G5 | GND(13) | | | G6 | VCCPINT(1) | | | G7 | VP_0 | | | G8 | VREFN_0 | | | G9 | TCK_0 | | | G10 | VCCINT(3) | | | G11 | IO_L1P_T0_34 | | | G12 | IO_L2P_T0_34 | | | G13 | GND(14) | | | G14 | IO_L3P_T0_DQS_PUDC_B_34 | | | G15 | IO_L5P_T0_AD9P_35 | | | H1 | PS_DDR_DQ14_502 | | | H2 | PS_DDR_DQ15_502 | | | H3 | PS_DDR_VRP_502 | | | H4 | RSVDVCC3 | | | H5 | VCCPINT(2) | | | H6 | GND(15) | | | H7 | VREFP_0 | | | H8 | VN_0 | | | H9 | VCCAUX(1) | | | H10 | GND(16) | | | H11 | IO_L6P_T0_34 | | | H12 | IO_L1N_T0_34 | | | H13 | IO_L2N_T0_34 | | | H14 | IO_L3N_T0_DQS_34 | | | H15 | VCCO_35(2) | | | J1 | PS_DDR_A10_502 | | | J2 | VCCO_DDR_502(4) | | | J3 | PS_DDR_VRN_502 | | | J4 | RSVDVCC2 | | | J5 | GND(17) | | | J6 | VCCPAUX(1) | | | J7 | DXP_0 | | | J8 | VCCAUX(2) | | | J9 | GND(18) | | | J10 | VCCINT(4) | | | J11 | IO_L6N_T0_VREF_34 | | | J12 | VCCO_34(1) | | | J13 | IO_L5P_T0_34 | | | J14 | IO_L5N_T0_34 | | | J15 | IO_L4P_T0_34 | | | K1 | PS_DDR_A14_502 | | | K2 | PS_DDR_A13_502 | | | K3 | PS_DDR_ODT_502 | | | K4 | GND(19) | | | K5 | VCCPINT(3) | | | K6 | PROGRAM_B_0 | | | K7 | GND(20) | | | K8 | VCCO_0 | | | K9 | VCCAUX(3) | | | K10 | GND(21) | | | K11 | IO_L11P_T1_SRCC_34 | | | K12 | IO_L11N_T1_SRCC_34 | | | K13 | IO_L10P_T1_34 | | | K14 | GND(22) | | | K15 | IO_L4N_T0_34 | | | L1 | GND(23) | | | L2 | PS_DDR_A11_502 | | | L3 | PS_DDR_CKE_502 | | | L4 | PS_DDR_DRST_B_502 | | | L5 | GND(24) | | | L6 | VCCPAUX(2) | | | L7 | TDI_0 | | | L8 | TDO_0 | | | L9 | TMS_0 | | | L10 | VCCINT(5) | | | L11 | GND(25) | | | L12 | IO_L12P_T1_MRCC_34 | | | L13 | IO_L10N_T1_34 | | | L14 | IO_L9P_T1_DQS_34 | | | L15 | IO_L8P_T1_34 | | | M1 | PS_DDR_A2_502 | | | M2 | PS_DDR_A12_502 | | | M3 | VCCO_DDR_502(5) | | | M4 | PS_DDR_A3_502 | | | M5 | PS_DDR_A7_502 | | | M6 | PS_DDR_BA0_502 | | | M7 | DONE_0 | | | M8 | GND(26) | | | M9 | IO_L19P_T3_34 | | | M10 | IO_L21P_T3_DQS_34 | | | M11 | IO_L21N_T3_DQS_34 | | | M12 | IO_L12N_T1_MRCC_34 | | | M13 | VCCO_34(2) | | | M14 | IO_L9N_T1_DQS_34 | | | M15 | IO_L8N_T1_34 | | | N1 | PS_DDR_A1_502 | | | N2 | PS_DDR_CKN_502 | | | N3 | PS_DDR_CKP_502 | | | N4 | PS_DDR_A9_502 | | | N5 | GND(27) | | | N6 | PS_DDR_BA2_502 | | | N7 | IO_L22P_T3_34 | | | N8 | IO_L22N_T3_34 | | | N9 | IO_L19N_T3_VREF_34 | | | N10 | VCCO_34(3) | | | N11 | IO_L13P_T2_MRCC_34 | | | N12 | IO_L13N_T2_MRCC_34 | | | N13 | IO_L7P_T1_34 | | | N14 | IO_L7N_T1_34 | | | N15 | GND(28) | | | P1 | PS_DDR_A0_502 | | | P2 | GND(29) | | | P3 | PS_DDR_A4_502 | | | P4 | PS_DDR_A5_502 | | | P5 | PS_DDR_A6_502 | | | P6 | PS_DDR_A8_502 | | | P7 | VCCO_34(4) | | | P8 | IO_L23P_T3_34 | | | P9 | IO_L23N_T3_34 | | | P10 | IO_L24P_T3_34 | | | P11 | IO_L16P_T2_34 | | | P12 | GND(30) | | | P13 | IO_L18P_T2_34 | | | P14 | IO_L18N_T2_34 | | | P15 | IO_L15P_T2_DQS_34 | | | R1 | PS_DDR_BA1_502 | | | R2 | PS_DDR_CS_B_502 | | | R3 | PS_DDR_WE_B_502 | | | R4 | VCCO_DDR_502(6) | | | R5 | PS_DDR_CAS_B_502 | | | R6 | PS_DDR_RAS_B_502 | | | R7 | IO_L20P_T3_34 | | | R8 | IO_L20N_T3_34 | | | R9 | GND(31) | | | R10 | IO_L24N_T3_34 | | | R11 | IO_L16N_T2_34 | | | R12 | IO_L17P_T2_34 | | | R13 | IO_L17N_T2_34 | | | R14 | VCCO_34(5) | | | R15 | IO_L15N_T2_DQS_34 | | --- *Generated from [https://www.flux.ai/jecstronic/xc7z010-3clg225e](https://www.flux.ai/jecstronic/xc7z010-3clg225e)*