LoRa PLC Receiver PCB


Created the detailed Project Specification and Preliminary BOM, including architecture, fail-safe COM–NC communications alarms, power budget, interfaces, PCB/enclosure requirements, verification criteria, recommended MPNs, and alternatives. Remaining work is final datasheet/availability verification for the radio SKU, relays, power supply, antenna certification conditions, Siemens input module, and enclosure; further execution is paused because no ACUs are currently available.
Can you do schematic for the transmitter and reciever
Yes. I’ll create two complete schematics: the existing 24 V PLC receiver and a matching field transmitter, using the established EU868/fail-safe requirements. I’ll first recover the saved specification and transmitter details, then build each board block-by-block and independently verify the finished schematics before layout.
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EU868 PLC Receiver Schematic
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The requirements are now reconciled across both projects. The receiver will use energized-healthy COM–NC communications alarms, while the transmitter will use two precision bridge channels and the same external-antenna EU868 radio family; both schematic builds are underway in parallel.
I recovered and reconciled the requirements for both boards and completed build passes in their respective projects:
  • Receiver: 24 V input, EU868 radio with external antenna, ten Form-C relay channels, eight COM–NO reel alarms, and two energized-healthy COM–NC communications alarms.
  • Transmitter: protected 24 V input, two precision load-cell bridge channels, STM32-class controller, EU868 radio with external antenna, programming and commissioning interfaces.
Both build processes report completion, but I could not inspect their final reports or independently verify schematic/ERC status. Therefore, the schematics should be treated as unverified until component counts, connectivity, power calculations, footprints, and ERC results are checked. PCB layout has not been started.
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Design Notes
Selected Architecture
The detailed architecture, preliminary power budget, interfaces, verification criteria, and open design selections are maintained in the Project Specification and Preliminary BOM project files.
Output Allocation
  1. Reel 1 low
  2. Reel 1 depleted
  3. Reel 2 low
  4. Reel 2 depleted
  5. Reel 3 low
  6. Reel 3 depleted
  7. Reel 4 low
  8. Reel 4 depleted
  9. Transmitter A communications fault
  10. Transmitter B communications fault
Relay Energization Logic
  • Reel/process outputs K1–K8: relay is normally de-energized; an alarm energizes the relay and closes COM-NO.
  • Communications outputs K9–K10: healthy state energizes the relay and opens COM-NC. Boot, reset, firmware lockup, missed external-watchdog service, unhealthy radio link, loss of 3.3 V logic, loss of 5 V coil power, or total receiver power loss de-energizes the relay and closes COM-NC to signal an alarm.
  • Firmware provides an independent recurring service pulse for each communications watchdog only while the corresponding transmitter link is healthy.
  • The receiver is an operational monitor and these outputs are not safety-rated.
Preliminary Power Result
  • 5 V rail design peak: approximately 630 mA including ten relays, 3.3 V conversion, indicators, and margin.
  • 5 V regulator target: at least 1.0 A, preferably 1.5 A with 60 V-class input tolerance.
  • 3.3 V design peak: approximately 190 mA, dominated by LoRa transmit current.
  • 3.3 V regulator target: at least 300 mA with thermal capability for approximately 0.32 W preliminary worst-case dissipation.
  • Selected Architecture

  • Output Allocation

  • Relay Energization Logic

  • Preliminary Power Result