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Board Bring-Up Plan — LVDS Differential PCB
Prerequisites
  • Equipment: current-limited 3.3 V supply, multimeter, oscilloscope with differential probe if available, signal generator or 3.3 V logic source.
  • Safety: power the board from VCC_LVDS at 3.3 V only; DS90LV049 recommended operating supply is 3.0–3.6 V.
1. Visual Inspection
  • Verify U1 DS90LV049TMTX orientation and solder joints.
  • Verify C1 100 nF and C2 1 uF are populated near U1.
  • Verify RTERM is 100 Ω across LVDS_P and LVDS_N.
  • Verify headers J1, J2, and J3 match the documented pinout.
2. Power Rail Verification

Table

RailSourceExpected VoltageMeasure AtCurrent LimitPass Criteria
VCC_LVDSJ3:1 or J1/J2:13.3 VU1:VDD, C1:P1, C2:P1100 mA initial3.0–3.6 V, no excessive current
GNDJ3:2, J1/J2:20 VU1:GND, C1:P2, C2:P2—Continuity to all GND pins
Procedure:
  1. With power off, measure resistance from VCC_LVDS to GND; confirm no short.
  2. Apply 3.3 V with a 100 mA current limit.
  3. Measure U1:VDD to U1:GND.
  4. Check C1/C2 supply pins for the same voltage.
3. Critical Signal Verification

Table

SignalNetExpected StateMeasure AtNotes
EnableVCC_LVDS via U1:ENHighU1:ENEnables outputs
Active-low enableGND via U1:~{EN}LowU1:~{EN}Enables outputs
Logic inputLOGIC_DIN13.3 V logicJ3:3, U1:DIN1Drives LVDS pair
Logic outputLOGIC_ROUT13.3 V logicJ3:4, U1:ROUT1Receiver monitor output
LVDS positiveLVDS_PLVDS differentialJ1:3, J2:3, RTERM:P1100 Ω differential pair
LVDS negativeLVDS_NLVDS differentialJ1:4, J2:4, RTERM:P2100 Ω differential pair
4. Connector and Interface Tests

Table

ConnectorPins to VerifyTest Method
J1 LVDS header1 VCC_LVDS, 2 GND, 3 LVDS_P, 4 LVDS_NContinuity to nets
J2 LVDS header1 VCC_LVDS, 2 GND, 3 LVDS_P, 4 LVDS_NContinuity to nets
J3 logic header1 VCC_LVDS, 2 GND, 3 LOGIC_DIN1, 4 LOGIC_ROUT1, 5 EN, 6 ~EN tied lowContinuity and logic-level measurement
5. Functional Validation

Table

TestInputExpected OutputPass Criteria
Driver pathToggle J3:3 (LOGIC_DIN1)Differential activity on LVDS_P/LVDS_NDifferential waveform visible across RTERM
Receiver monitorDifferential activity on LVDS_P/LVDS_NJ3:4 (LOGIC_ROUT1) togglesLogic output follows receiver state
TerminationMeasure across LVDS_P/LVDS_N unpowered~100 Ω95–105 Ω for 1% resistor
Pass/Fail Summary

Table

SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Connector Pinout[ ] Pass / [ ] Fail
LVDS Functional Test[ ] Pass / [ ] Fail
Board Status: [ ] Ready for layout/routing update / [ ] Requires schematic rework

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Connector and Interface Tests

  • 5. Functional Validation

  • Pass/Fail Summary