ESP32 Robotics Controller
5V_MAIN. Eight MP5073 eFuses create independently enabled, current-limited 5 V docking outputs. An AP63203 buck generates 3.3 V for the ESP32-S3, indicators, protection logic, and TCA9548A I²C mux. The ESP32 has eight dedicated ADC1/LEDC-capable SIG lines, while the mux isolates one SDA/SCL pair for each magnetic docking port.Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| J1 | GCT USB4105-GF-A, USB-C receptacle | Brings in VBUS, CC1/CC2, and USB 2.0 D+/D−; provides the single external power/programming interface. | Documented: shared USB-C for PD power and ESP32 native USB, centered at the top edge. The selected connector supports the required USB-C contacts and board-edge mechanical interface. | Connector shell/ground return and differential-pair breakout are layout-critical. Mechanical edge placement must match the enclosure/cable. |
| U1 | WCH CH224K | Negotiates USB-PD and requests a fixed 20 V profile; its PG output indicates a valid contract. | Documented: CFG code 010 (CFG1=0, CFG2=PD_VDD, CFG3=0) selects 20 V, enabling efficient high-power conversion instead of distributing high current at 5 V. | The source and cable must actually advertise a suitable 20 V PDO. Available current is contract-dependent. |
| R1 | 1 kΩ, 0805, 0.5 W, generic resistor | Feeds the CH224K internal/shunt-derived PD_VDD supply from VBUS while limiting current and dissipating the voltage drop. | Documented: follows the CH224K reference circuit. The larger 0805/0.5 W selection addresses dissipation from a 20 V input. | No manufacturer/MPN assigned; verify worst-case resistor dissipation and pulse behavior before production. |
| R2 | 10 kΩ, 0603, generic resistor | Series-limits the CH224K VBUS-sense input. | Documented: isolates/limits the high-voltage sense path used by the PD controller. | No manufacturer/MPN assigned; verify tolerance requirement before production. |
| C1 | 1 µF, 10 V, 0603, generic capacitor | Local PD_VDD bypass for U1, preventing protocol/control instability from supply transients. | Documented: CH224K datasheet support capacitor. | Place directly at U1 VDD/GND. No MPN; verify dielectric and DC-bias behavior. |
| F1 | WALTER 2410F 3A 250V | Series fuse between raw negotiated VBUS and protected 20V_PD; protects against sustained input-path faults. | Documented: 3 A input protection is consistent with the recommended 20 V/3 A adapter and ~1.89 A expected input at 34 W/90%. | It does not enforce a precise 5 V output limit. Verify time-current curve, inrush survival, and PCB heating. Extended/JLCPCB part. |
| D1 | Taiwan Semiconductor SMBJ24A-TR | TVS clamps transients on the protected 20 V PD rail. | Documented: 24 V standoff avoids normal conduction at the intended 20 V contract while providing surge protection. | Keep the surge loop short and route to a low-inductance ground return. Confirm clamp coordination with downstream absolute maximums. |
| C2, C3 | 22 µF, 35 V, 1210, generic capacitors | Bulk energy storage on 20V_PD; reduces adapter/cable impedance effects and supplies converter input transients. | Documented: two capacitors provide protected-rail bulk capacitance with voltage margin above 20 V. | MLCC effective capacitance falls with DC bias. No MPN; verify dielectric, ripple current, inrush, and USB-PD source compatibility. |
Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| U2 | Texas Instruments LM5148RGYR | Controls the external high-side/low-side MOSFETs as a synchronous buck from 20V_PD to 5V_MAIN; regulates output and monitors inductor current through RS1. | Documented: selected for the high-current 20 V→5 V architecture that an integrated low-current regulator cannot support. External MOSFETs and current sensing suit the 8 A-class target. | Current-limit onset is estimated 7.34–11.79 A (9.40 A typical), not a guaranteed ceiling. Compensation, Kelvin sensing, thermal copper, and switch-loop placement are critical. |
| Q1 | Alpha & Omega AONS66614, 60 V N-MOSFET, DFN 5×6 | High-side switch connecting 20 V input to the switching node. | Documented: low-RDS(on), 60 V external MOSFET provides efficiency and transient voltage margin for the high-current stage. | Gate loop and hot-loop inductance must be minimized; verify switching loss and junction temperature. |
| Q2 | Alpha & Omega AONS66614, 60 V N-MOSFET, DFN 5×6 | Low-side synchronous rectifier, replacing a lossy catch diode. | Documented: same MOSFET simplifies sourcing and minimizes conduction loss at high output current. | Prevent shoot-through; provide strong thermal vias/copper and short PGND return. |
| L1 | Würth 744311150, 1.5 µH ±20%, 11 A rated | Stores energy and filters switch-node current into the 5 V rail. | Documented: chosen for the ~2.1 MHz, 20 V→5 V design; calculated ripple is about 1.19 A p-p nominal. | 14 A saturation at 30% inductance drop is typical, not a guaranteed short-current limit. Validate temperature rise and saturation margin. |
| RS1 | Vishay WSLP12066L000FEA, 6 mΩ ±1%, 1 W | Current shunt for LM5148 cycle/current-limit sensing. | Documented: real, sourceable 6 mΩ part replacing an unsupported shunt; sets the present current-limit-onset range. | Requires true Kelvin routing to U2 ISNS+/VOUT sense pins; package and dissipation affect accuracy. |
| R3 | 9.53 kΩ ±1%, 0603, generic | Programs U2 switching frequency. | Documented: selected for approximately 2.1 MHz, reducing magnetic size and supporting the chosen reference design. | Frequency affects losses, ripple, and current-limit calculations. No MPN; verify tolerance/tempco. |
| R4 | 24.9 kΩ ±1%, 0603, generic | Connects FB to VDDA to select the LM5148 fixed 5 V option. | Documented: directly selects the required 5V_MAIN voltage. | Treat as a precision configuration component; keep away from SW copper. No MPN. |
| R5 | 24.9 kΩ ±1%, 0603, generic | Programs the LM5148 CNFG function. | Documented: value copied from the selected LM5148 reference design. | Exact operating-mode implications should be rechecked against the final datasheet revision—verify before production. No MPN. |
| R6, C13 | 10 kΩ ±1% and 2.7 nF, both 0603, generic | External Type-II compensation network stabilizes the control loop and shapes transient response. | Documented: values taken from the LM5148 reference design used for this power stage. | Must be placed adjacent to EXTCOMP/AGND and isolated from SW. Stability should be validated with final PCB/load/capacitance—verify before production. |
| R7, R8 | 100 kΩ / 10 kΩ, ±1%, 0603, generic | EN/UVLO divider controls when the main buck starts, preventing operation below the intended input region. | Documented function; inferred rationale: divider provides deterministic startup only after a valid high-voltage PD rail exists. | Threshold must be recomputed with U2 tolerances and actual PD ramp—verify before production. No MPNs. |
| C4, C5 | Samsung CL32B475KBUYNNE, 4.7 µF ±10%, 50 V X7R, 1210 | High-frequency input bypass near U2/power MOSFET stage. | Documented: 50 V rating provides input transient margin; 1210 package preserves more effective capacitance than smaller MLCCs. | Extended/JLCPCB part. Place across the smallest VIN–PGND hot loop; account for DC-bias derating. |
| C6, C7, C8, C9 | 10 nF, 50 V, 0603, generic | Very local high-di/dt input capacitors at the MOSFET half bridge, suppressing ringing and loop inductance effects. | Documented: four small capacitors distribute high-frequency bypassing around the power stage. | Placement is more important than nominal bulk value. No MPNs; use suitable C0G/X7R voltage-rated parts. |
| C10 | 100 nF, 10 V, 0603, generic | U2 VDDA-to-AGND decoupling. | Documented: keeps analog control/sense supply quiet despite the noisy switch stage. | Place at VDDA/AGND pins, not through power-ground return. No MPN. |
| C11 | 2.2 µF, 10 V, 0805, generic | U2 gate-driver VCC bypass to PGND, supplying peak gate current. | Documented: local reservoir for external MOSFET switching. | Very short VCC–PGND loop required; verify effective capacitance. No MPN. |
| C12 | 100 nF, 16 V, 0603, generic | Bootstrap capacitor from CBOOT to SW powers the high-side gate driver. | Documented: standard LM5148 bootstrap element. | Place directly between pins; voltage stress and gate-charge sizing should be confirmed. No MPN. |
| C14, C15, C16, C17 | Murata GRM32ER71A476KE15L, 47 µF, 10 V X7R, 1210 | Four-capacitor output bank filters ripple and supplies actuator/load transients on 5V_MAIN. | Documented: four-device LM5148 reference bank provides high effective capacitance and ripple sharing for the high-current rail. | Effective capacitance at 5 V, RMS ripple, anti-ferroelectric effects, and mechanical cracking risk must be considered. |
Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| U3 | Diodes Incorporated AP63203WU-7, fixed 3.3 V synchronous buck | Converts 5V_MAIN to the logic 3V3 rail for ESP32, mux, LEDs, and eFuse controls. | Documented: separate regulator prevents logic from relying directly on the noisy actuator rail and supports a reserved ~0.8 A operating allocation with transient margin. | Firmware must still enforce aggregate loading. Keep switch loop compact and protect logic rail from actuator ground bounce. |
| L2 | 3.9 µH, 3 A rated, 3.5 A saturation, SMD_6045, generic | Output energy-storage/filter inductor for U3. | Documented: recommended 3.9 µH value with ≥3 A capability for the 2 A-class regulator. | No manufacturer/MPN; saturation, DCR, dimensions, EMI, and thermal rise must be qualified—verify before production. |
| C18 | 10 µF, 10 V, 0805, generic | U3 input bypass from 5 V. | Documented: required regulator input capacitor, reducing local input ripple. | Place next to VIN/GND. No MPN; verify effective capacitance. |
| C19, C20 | 22 µF each, 6.3 V, 0805, generic | Parallel output capacitors stabilize and provide transient energy on 3.3 V. | Documented: two capacitors implement the U3 output network and improve Wi-Fi/load-step support. | 6.3 V rating has limited margin and MLCC DC-bias derating may be significant. No MPNs. |
| C21 | 100 nF, 16 V, 0603, generic | Bootstrap capacitor between U3 BST and SW. | Documented: required high-side driver supply component. | Place immediately at U3. No MPN. |
Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| U12 | Espressif ESP32-S3-WROOM-1-N8R8 | Main controller; provides Wi-Fi/BLE, native USB, eight port SIG GPIOs, I²C mux control, enables, monitoring, and firmware power scheduling. | Documented: N8R8 provides 8 MB flash/8 MB PSRAM and sufficient GPIO/peripherals. SIG map is GPIO1,2,4,5,6,7,8,9; I²C is GPIO39/40; mux reset is GPIO10; USB is GPIO19/20. | RF antenna keep-out must remain free of copper/components on every layer. GPIO35–37 are unavailable with Octal PSRAM. Confirm firmware pin ownership and boot strapping. |
| C22 | 22 µF, 6.3 V, 0805, generic | Local 3.3 V bulk reservoir for ESP32 radio/CPU transients. | Documented: supports high peak current during Wi-Fi/BLE activity. | Place near module 3V3 pins; no MPN; verify DC-bias capacitance. |
| C23 | 100 nF, 6.3 V, 0603, generic | High-frequency ESP32 supply bypass. | Documented: complements C22 for local fast transient current. | Place directly at module supply/ground. No MPN. |
| R9, C24 | 10 kΩ pull-up and 1 µF, 6.3 V, both 0603 generic | Forms the ESP32 EN power-on/reset RC and ensures EN defaults high. | Documented: follows ESP32 hardware guidance for reliable power-on reset. | Reset timing depends on tolerances/leakage. Keep EN protected from noisy power switching. No MPNs. |
| R10 | 10 kΩ, 0603, generic | Pulls GPIO0 high for normal SPI boot. | Documented: establishes the required default boot state. | Button/USB download behavior must not violate strap sampling. No MPN. |
| SW1 | Panasonic EVQ-P7J01P | Momentarily pulls ESP32 EN low to reset the controller. | Documented: side-accessible RESET control. | Mechanical access/orientation and debounce are system considerations. |
| SW2 | Panasonic EVQ-P7J01P | Momentarily pulls GPIO0 low for download/bootloader entry. | Documented: side-accessible BOOT control for native USB programming/recovery. | Must be used with reset sequencing; verify enclosure access. |
Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| D2 | STMicroelectronics USBLC6-2SC6 | Low-capacitance ESD array protects USB D+/D− between J1 and U12. | Documented: protects the external high-speed data interface without the capacitance of a general-purpose TVS. | Place close to J1 with short ground path; preserve differential-pair symmetry and controlled impedance. |
| R11, R12 | 22 Ω ±1%, 0402, generic | Series source damping in ESP32 native USB D+/D− paths; reduces ringing/edge-rate reflections. | Documented: placed near the ESP32 as USB source damping. | Final need/value depends on routed impedance and ESP32 guidance. Route as a matched pair; no MPNs—verify before production. |
Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats / layout / sourcing |
|---|---|---|---|---|
| U13 | Texas Instruments TCA9548APWR | Eight-channel I²C switch maps CH0–CH7 to ports 1–8 and isolates deselected downstream buses. | Documented: solves same-address EEPROM conflicts and prevents a stuck-low device on a deselected port from blocking the controller bus. Address is 0x70; reset is GPIO10-controlled. | Modules must use 3.3 V SDA/SCL, not 5 V. Firmware should normally enable one channel at a time. |
| C49 | Samsung CL10B104KB8NNNC, 100 nF, 10 V, 0603 | Local U13 VCC bypass. | Documented: supplies switching transients and stabilizes the mux logic rail. | Place directly at U13 VCC/GND. |
| R36 | Stackpole RMCF0603FT10K0, 10 kΩ ±1%, 0603 | Pulls TCA9548A active-low RESET high while allowing GPIO10 to assert reset. | Documented: ensures the mux is released by default but remains firmware-resettable. | Reset assertion must be open-drain or otherwise avoid contention with 3.3 V. |
| R13, R14 | Yageo RC0603FR-074K7L, 4.7 kΩ, 0603 | Sole upstream pull-ups for I2C_MUX_SDA and I2C_MUX_SCL. | Documented: one pull-up pair prevents unintended parallel loading and supports the short 3.3 V controller bus. | Rise time must be measured after routing; intended for typical 100–400 kHz use. |
| R37–R52 | Yageo RC0603FR-074K7L, 4.7 kΩ ±1%, 0603 | One SDA/SCL pull-up pair per isolated downstream channel. Explicit map: P1 R37/R38; P2 R39/R40; P3 R41/R42; P4 R43/R44; P5 R45/R46; P6 R47/R48; P7 R49/R50; P8 R51/R52. | Documented: each deselected channel retains a defined 3.3 V idle state without paralleling all 16 resistors onto the upstream bus. | If multiple channels are enabled simultaneously, pull-ups become effectively parallel through U13. Measure bus capacitance/rise time—verify before production. |
Table
| Port | Components and exact values | Electrical role / problem solved | Design rationale and caveats |
|---|---|---|---|
| 1 | U4 MP5073GG-Z; R17 15 kΩ ±1% ILIM; R25 100 kΩ EN pull-down; C25 100 nF 6.3 V SS; C33 1 µF 10 V input bypass; C41 10 µF 10 V output bulk; D11 BAT54H,115 PG-OR diode; D3 ESDA6V1BC6; R37/R38 4.7 kΩ SDA/SCL; JPORT1 PR5L5015-5P-C-H | Independently switches and limits PORT1_5V, defaults disabled, ramps output, reports fault into PORT_FAULT_N, protects SIG/SDA/SCL from ESD, and connects 5 V/GND/SIG/SDA/SCL. | Documented: MP5073 is nominal 2 A-class protection; 15 kΩ programs about 2.2 A typical. Connector pins: 1=5V, 2=GND, 3=SIG, 4=SDA, 5=SCL. ESD return and eFuse thermal copper are layout-critical. |
| 2 | U5; R18 15 kΩ; R26 100 kΩ; C26 100 nF; C34 1 µF; C42 10 µF; D12 BAT54H,115; D4 ESDA6V1BC6; R39/R40 4.7 kΩ; JPORT2 | Same functions for PORT2_5V, PORT2_SIG, PORT2_SDA/SCL. | Same documented topology and caveats as Port 1; mapping remains channel-specific and isolated through U13 CH1. |
| 3 | U6; R19 15 kΩ; R27 100 kΩ; C27 100 nF; C35 1 µF; C43 10 µF; D13 BAT54H,115; D5 ESDA6V1BC6; R41/R42 4.7 kΩ; JPORT3 | Same functions for Port 3. | U13 CH2; connector physical pin mapping is fixed as above. Verify protected SIG misuse limits before production. |
| 4 | U7; R20 15 kΩ; R28 100 kΩ; C28 100 nF; C36 1 µF; C44 10 µF; D14 BAT54H,115; D6 ESDA6V1BC6; R43/R44 4.7 kΩ; JPORT4 | Same functions for Port 4. | U13 CH3. Per-port eFuse protection does not enforce the global 6.8 A allocation. |
| 5 | U8; R21 15 kΩ; R29 100 kΩ; C29 100 nF; C37 1 µF; C45 10 µF; D15 BAT54H,115; D7 ESDA6V1BC6; R45/R46 4.7 kΩ; JPORT5 | Same functions for Port 5. | U13 CH4. Keep output capacitor/eFuse/connector current path short and wide. |
| 6 | U9; R22 15 kΩ; R30 100 kΩ; C30 100 nF; C38 1 µF; C46 10 µF; D16 BAT54H,115; D8 ESDA6V1BC6; R47/R48 4.7 kΩ; JPORT6 | Same functions for Port 6. | U13 CH5. Validate connector/contact heating at sustained current. |
| 7 | U10; R23 15 kΩ; R31 100 kΩ; C31 100 nF; C39 1 µF; C47 10 µF; D17 BAT54H,115; D9 ESDA6V1BC6; R49/R50 4.7 kΩ; JPORT7 | Same functions for Port 7. | U13 CH6. Shared diode-OR fault gives aggregate rather than per-port telemetry. |
| 8 | U11; R24 15 kΩ; R32 100 kΩ; C32 100 nF; C40 1 µF; C48 10 µF; D18 BAT54H,115; D10 ESDA6V1BC6; R51/R52 4.7 kΩ; JPORT8 | Same functions for Port 8. | U13 CH7. UART0 remains free; PORT8_SIG uses ESP32 GPIO9 rather than a UART pin. |
5V_MAIN bypass for each eFuse input. No MPNs assigned.PORT_FAULT_N without tying push-pull outputs together. The topology reports “one or more ports faulted,” not which port.Table
| Designator(s) | Exact part/value | Electrical function and problem solved | Selection rationale | Caveats |
|---|---|---|---|---|
| LED1 | Rohm SML-D13FWT86C, green 0603 LED | Indicates presence of the 3.3 V rail. | Documented: always-on power indication gives immediate logic-rail bring-up feedback. | Schematic part property incorrectly shows designator prefix “R”; actual designator is LED1. Verify polarity in footprint. |
| R15 | 1 kΩ, 0603, generic | Limits LED1 current from 3.3 V. | Documented: low indicator current reduces continuous logic-rail load. | No MPN; actual brightness depends on LED Vf/bin. |
| LED2 | Würth 150060BS73220, blue 0603 LED | GPIO-driven system/status indicator. | Documented: gives firmware-controlled state/fault/activity feedback distinct from power LED. | Verify GPIO polarity and desired brightness. |
| R16 | 330 Ω, 0603, generic | Limits LED2 GPIO current. | Documented: higher current than the power LED supports visible blue indication. | Check ESP32 GPIO current and LED Vf across tolerance. No MPN. |
| SW1, SW2 | Panasonic EVQ-P7J01P | RESET and BOOT user controls; detailed in Section 4. | Documented: side-accessible service/programming controls. | Mechanical accessibility must be checked in enclosure. |
Table
| Designator(s) | Exact part/value | Function / rationale | Caveats |
|---|---|---|---|
| R33 | 10 kΩ, 0603, generic | Pulls diode-combined PORT_FAULT_N high so any BAT54H-connected active-low PG can assert a shared fault. Documented: provides aggregate port-fault monitoring with low GPIO use. | Shared fault telemetry does not identify the channel. No MPN. |
| R34 | 10 kΩ, 0603, generic | Pull-up from open-drain MAIN_PG to 3.3 V. Documented/inferred: level-translates the main converter status into ESP32 logic and provides a defined high state. | Confirm U2 PG voltage/current compatibility and MCU assignment. No MPN. |
| R35 | 10 kΩ, 0603, generic | Pull-up from CH224K PD_PG to 3.3 V. Documented/inferred: lets firmware detect a valid PD contract using 3.3 V logic. | Confirm PG output type and startup sequencing. No MPN. |
System architecture overview
Subsystem index
1. USB-C / PD input and input protection
2. 20 V to 5 V main converter
3. 3.3 V rail
4. ESP32-S3 control and boot/reset support
5. USB data protection and damping
6. I²C mux and isolated downstream buses
7. Eight protected docking-port channels
Repeated-part selection details
8. Indicators and buttons
9. Connectors and external interfaces
10. Miscellaneous support and power monitoring
Design-wide caveats
11. Coverage appendix — all current designators
12. Parts with missing manufacturer/MPN data